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  1. A

    assign a value to output

    I have this code i just want the output of pim to be any integer value after 100s what should be done.. The value in t should be assinged to pim which is displayed on the waveform irrespective of the inputs module wave(mode,p,x,clk,pim); input [1:0]mode; input [3:0]p; input [7:0]x; input clk...
  2. A

    System is not syhtesizing

    module system(clk,mode,x,p,pim); parameter elements = 10; //This is the number of processing elements we want to have it in our design. input clk; input [1:0]mode; input [7:0]x; input [3:0]p; output [3:0]pim; wire [elements:0] conti; wire [elements:0] contx; wire [elements:0]...
  3. A

    The simulation results are not coming..

    module pe3(clk,i,x,p,psw,psyi,mode,io,xo,po,pswo,psyo); //Here evey where PE refers to the PROCESSING ELEMENT parameter divfac=128; //The factor used to implement decimal multipication of learn rate and weight. parameter size =1; //The Image size or the number of pixels in the image...
  4. A

    Searching in a memory array

    How can we code in verilog to find a minimum value in a array .
  5. A

    Schematic Diagram of Synthesized Code

    module system(clk,mode,x,p,pim); parameter elements = 10; //This is the number of processing elements we want to have it in our design. input clk; input [1:0]mode; input [7:0]x; input [3:0]p; output [3:0]pim; wire [elements:0] conti; wire [elements:0] contx; wire [elements:0]...
  6. A

    How to incorporate Block RAM in our code...

    I am presently using registers as memory elements in my code . No since I need little large memory so i want to use block RAM, I found a block RAM in Xilinx core generator but i need toknow how do we incorporate it in our code.
  7. A

    Generate Loop in Verilog 2001

    Pls give me an idea if there is a module which i need to instantiate in a generate for loop such as outputs of the first instant shall go as an input to the next instant.If u could show me by the help of a small example its shall be good.
  8. A

    Simulation not giving results ...correctly

    pls see the output of the signal "pswo" module pe(clk,i,x,p,psw,psy,mode,io,xo,po,pswo); parameter size = 10;//The Image size or the number of pixels in the image //Input ports of the PROCESSING ELEMENT input clk; input [7:0]i;//Index of the input pixel input [7:0]x;//Value of the pixel input...
  9. A

    Can decimal numbers be used for simulation purpose

    can decimal or real values be used in simulation purpose.
  10. A

    Taking long time to synthesize WHY??

    module pe(clk,i,x,p,psw,psy,mode,io,xo,po,pswo); parameter size = 65535;//The Image size or the number of pixels in the image //Input ports of the PROCESSING ELEMENT input clk; input [7:0]i;//Index of the input pixel input [7:0]x;//Value of the pixel input input [3:0]p;//The Index of the...
  11. A

    Pls tell me the errors in this code

    module pe(clk,i,x,p,psw,psy,mode,io,xo,po,pswo); parameter size = 65535;//The Image size or the number of pixels in the image //Input ports of the PROCESSING ELEMENT input clk; input [7:0]i;//Index of the input pixel input [7:0]x;//Value of the pixel input input [3:0]p;//The Index of the...
  12. A

    Is it part of a code synthesizable?

    module out2(clk,j,w,y,xi,psw,w2); parameter lrate= 0.1; input [7:0]j; input [12:0]y ; input [7:0] xi; input [4:0] w ; input [4:0]psw; input clk; reg [12:0]d; reg [20:0]out; reg [20:0]temp; reg [20:0]temp1; reg [15:0]y2; reg [20:0]w1; output [20:0]w2; wire [20:0]w2...
  13. A

    Pls tell the errors in this code

    module pe(clk,lrate,i,x,p,psw,psy,mode,io,xo,po,pswo); parameter size = 65535;//The Image size or the number of pixels in the image input lrate; //The learning rate of the algorithm wire lrate; //Input ports of the PROCESSING ELEMENT input clk; input [7:0]i;//Index of the input pixel input...
  14. A

    Please have look at this code and tell me

    How to put the clock in this code. and is this a simple correct way to write code. module pe(clk,lrate,i,x,p,psw,psy,mode,io,xo,po,pswo); parameter size = 65535; input lrate; wire lrate; //Input ports of the PROCESSING ELEMENT input clk; input [7:0]i;//Index of the input pixel input...
  15. A

    is this a decent code of verilog to synthesize

    module out2(clk,j,lrate,w,y,xi,psw,g,w1); input lrate; input [7:0]j; input [7:0]y ; input [7:0] xi; input [7:0] w ; input [7:0]psw; input clk; wire [15:0]d; wire [23:0]out; wire [23:0]temp; wire [23:0]temp1; wire [15:0]y2; output [23:0]g; output [23:0]w1; assign d =...
  16. A

    Whats the problem with this code///

    module out2(j,w,y,xi,psw,g,w1); input [7:0]j; input [15:0] y; input [7:0] xi; input [23:0] w ; input [23:0]psw; wire [15:0]d; wire [23:0]out; wire [23:0]temp; wire [23:0]temp1; wire [15:0]y2; reg [7:0]k; output [23:0]g; output [23:0]w1; integer i; initial begin temp1 = 0...
  17. A

    Implement Synthesizable Decimal Arithmatic in Verilog

    verilog integers decimal How to implement decimal arithmatic in verilog which is synthesizable..
  18. A

    How can we pass a decimal value in the module Verilog

    I need to pass a value of o.o1 to module and it gets multiplied to some value inside. Now if idefine it as a parameter it does not get implemented. what to do.
  19. A

    Is the parameter key word synthesizable ?

    is the parameter key word synthesizable
  20. A

    My Verilog code is giving arbid error pls see

    verilog error-[ind] module pelement(ii, xi, pi, psi, clk, m1, m2, io, xo, po, psj); //Parameters Learning Rate of the Neural network parameter lrate = 1; //Input ports of the processing element input [5:0] ii; //Index of the pixel input to the processing element input [7:0]...

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