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  1. N

    The output voltage of Boost circuit is very high

    Thanks a lot! This is thing I need!
  2. N

    How to design current limit circuit (0.25um technology)?

    Hi everyone, I want to design a current limit circuit (feedback from output of BOOST circuit). Vin: 3.3v -> 5.5v Output: 10v, 20mA Can anyone help me? Thanks!
  3. N

    Setup license for IC 6.1 of Cadence

    Setup license for IC 6.1 I installed IC6.1 of Cadence but i didn't how to set up license file. The warning message of ICFB is: ""*WARNING*(icLic-3) COULD NOT GET THE LICENSE Virtuaso_Schematic_Editor_L (deLicense-3)COULD NOT GET THE LICENSE Schematic_L.Trying a higher_tiered license...". I...
  4. N

    Novas Debussy license file

    debussy license Help me! I have Novas Debussy v5.3.09 software but I lost license file. Anyone can give me this file (license)? Regards! Thanks.
  5. N

    Bandgap vout=1.8v, help me!!!

    coi file nay
  6. N

    Where can I get the nWave tool for Windows?

    I need a nWave for Win, please tell me a link to down it, thanks.
  7. N

    Buck-Boost: Vout=-10V, Iout=20mA ???

    I'm on project about Buck-Boost regulator. I've just reached Vout=-7V.I need Vout=-10V, Iout=20mA. Anyone can help me? Regards!
  8. N

    Convert Assura to Dracula DRC file

    Hi everybody! I have Assura DRC file, but my Cadence can use Dracula. And I want to convert Assura file to Dracula. May anyone help me? Thanks...
  9. N

    Looking for detailed schematic of FDC6305N and SI2306DS

    Boost converter Hi! I've parameters of FDC6305N model.I need a schematic of (W,L) parameters of every MOS in it.Google search can't help me. Can you help me? Thanks!
  10. N

    Place & Route: I don't understand why?

    But I see lef file just rule for metal and via, not standard cell. May your idea is def file. Let me see... Thanks
  11. N

    Place & Route: I don't understand why?

    I have gate-level netlist.v and layout after run place&route, but I count block at layout different block at gate-level netlist. I don't understand why, anyone please help me. And what I must do to repair that... Thanks
  12. N

    Shutdown circuit for LDO???

    I need a shutdown crcuit for my LDO. Who can show me the paper or schematic? Thanks.
  13. N

    How to find file in Linux

    thank you very much. I will try
  14. N

    Looking for detailed schematic of FDC6305N and SI2306DS

    I'm on project with Boost converter. I'm looking for schematic of model: FDC6305N, SI2306DS. Anyone can help me? Thanks!
  15. N

    Converting Verilog to SPICE for LVS in dracula

    You import verilog netlist and then export cdl file, you can run LVS in dracula
  16. N

    How to find file in Linux

    Hi, I am using Linux and I need find file, but I don't see Find the same Window, anyone help me?
  17. N

    Can't repair error LVS, Urgent!

    Thanks for your reply. I will try
  18. N

    Can't repair error LVS, Urgent!

    Hi everybody! When I import gds file, I can't see instance name and net name, so I can't repair error. When I place and route with Encounter I see instance name, but I don't know why I can't see it in Vituoso. What must I do? I see in Soc_encounter tutorial have " Attach Instance Name" and...
  19. N

    Problem with importing Verilog to Cadence as it only creates symbol and functions

    Re: Help me! Hi letan! You should guide Verilog in at Cadence. If you want to have schematic then your verilog netlist is structural cell, not behavial cell, and .... I just read it because I don't know it right......

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