# Search results

1. ### How to deal with gated clock in Synopsys Formality?

Hello, I compiled some gated clocks in my design, and when I do formal verification, the gated clock cells are in unmatch cell list, how can I tell Formality about the gated clock setting? Regards,
2. ### How to get off some cells like "**SEQGEN**" in DC

Hello, I want to compile my design to gate-level with DC, but I always got some cells like **SEQGEN** in the netlist, I have no idea about the reason, that seems like I didn't finish the compiling, is the anyone knows that? Regrads,
3. ### How to stop simulation in VHDL testbench?

Hello, I don't know how to stop my simulation, my testbench is described in VHDL and I use ncsim, is there any method to stop the simulation just like using $stop,$finish in Verilog? Regards,
4. ### clock multiplexer problem - help needed

clock multiplexer Hello, I have two input clocks, CLKA and CLKB. They go to a multiplexer directly from input port then generate a new clock CLK_SYS as the system clock of the whole circuit, but the select signal of the clock multiplexer comes from the CLK_SYS domain and its value is not a...
5. ### Constraint on Multi-Clock with a same source

Hello guys, In my design, we have multiple clocks with different frequency, but the clocks have the same source. (For example, clock A and clock B both are divided from clock S, and Frequency(A) = n*Frequency(B), n is an integer) There are some logic between the two clock domains, how can I...
6. ### Constraint on combination logic in DC

set_output_delay in dc Hi all, I use Synopsys DC to compile my design, and in the design: A is the input, B is a sequential logic output of it, and C is a combinational logic output of it. In my constraint file, for sequential part, I set constraint like below: create_clock -period 20 -waveform...
7. ### DC_SHELL constraint about input delay and output delay

input delay and output delay Hi Guys, I am confused with the command "set_input_delay" and "set_output_delay": The clock frequency is 50MHz. For constraint on a path from input pin to a DFF, I want the logic between input pin and the DFF to take only 5 ns, should I use "set_input_delay -max...
8. ### Formality failed to read .svf file with syntax error report.

svf read Hi Guys, I meet an issue when I read .svf file with "set_svf ./svf_name.svf", that generated an error report: ################################## line 1: syntax error at 'c' Error: Invalid SVF, contents ignored (FM-339) 0 ################################## I generated my svf file...
9. ### How to convert a number string to several integer?

Hello, I want to convert a number string to several integer with VHDL language, for example: convert 1112131415 to 5 integer -- 11,12,13,14,15. Would anybody like to help me to solve that? Thanks!
10. ### A question about VHDL TEXTIO

vhdl textio Hello, I'm trying to read some stimulus form a file, but an error always occur, would you like to help me to solve it, thanks. Source code: library ieee; use ieee.std_logic_1164.all; use std.textio.all; entity FILE_READ is generic ( stim_file: string...
11. ### Several concept questions

Hi, I have several concept questions, pls tell me if u know them, thanks! 1. Domino Logic what is domino logic, and why call it "Domino". 2. What means "MOSIS" 3. Anybody can tell me about "In-Place Optimization". 4. "Insert netlist CT", what's CT? Have a good day!
12. ### A question about embeded microcontroller

I want to integrate an embeded mcu in my chip, I look up the soft IP list of some IP vendors, I find that they don't give the max clock frequency. I wonder if the work frequency of an embeded mcu depends on the foundry process? How can I configure the work clock of mcu due to my IC system? Thanks!
13. ### Microcontroller accesses EEPROM wiht I2C interface ?

I want to configrate my IC with an EEPROM, should I select which speed mode of I2C Bus? Does any EEPROM provide high-speed mode of I2C Bus? Thanks!