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  1. blueagate

    The wrapping burst operation of AMBA bus?

    wrapping burst Does anyone can explain the wrapping burst operation of AMBA bus in detail? Thanks.
  2. blueagate

    Mixed signal verification question with Nanosim + VCS

    The counter in Verilog HDL did not count because there was an unknown state in A2DCLK.
  3. blueagate

    Mixed signal verification question with Nanosim + VCS

    set_node_thresh I am debugging a mixed signal design by using Nanosim + VCS. The analog circuit is described in spice and the digital circuit is described in Verilog. A clock named A2DCLK is generated by analog circuit and feed to digital circuit. While A2DCLK rise from 0 to 3.3v, the...
  4. blueagate

    USB1.1 PHY Behavioral Model Needed

    I need a Behavioral Model of USB1.1 PHY which in Verilog or VHDL in order to test my USB code. Thanks.
  5. blueagate

    USB1.1 PHY Verilog or VHDL behavioral model needed

    usb1.1 design phy I am working a project with USB1.1, I need the USB1.1 PHY behavioral model in order to simulate the design. Please give me some information about USB1.1 PHY behavioral model. Thanks.
  6. blueagate

    Can Quartus convert a design to HDL?

    qu@rtus Hi, my friends, Quartus II can translate the sch to HDL, by using the Create/Update in the file menu, both full and free version support this.
  7. blueagate

    How to translate the Quartus II 4.0 project to Quartus II 3.

    How to translate the qu@rtus II 4.0 project to qu@rtus II 3. Hi, cube007, Because there is not anywhere have the Quartus II 4.0, some companys have both version 3.0 and 4.0 of Quartus II. I think that it will be convenient while transfer project from one computer to another if the solution...
  8. blueagate

    How to translate the Quartus II 4.0 project to Quartus II 3.

    Since the suffix of the project name of Quartus II 4.0 is .qpf, which is .quartus in Quartus II 3.0, Quartus II 3.0 can not open .qpf file directly. When using the Archive project from the Project Menu in Quartus II 4.0, and restore in Quartus II 3.0, the hierarchy of the project will be lost...
  9. blueagate

    How to make a cpu work correctly?

    Does someone have any documents about Lexra risc cpu? I need some paper for reference. Thanks.
  10. blueagate

    How to make a cpu work correctly?

    I am making a test board based MIPS, I have read some MIPS documents. I think that most documents tell me how to write the software, but I want know more about the hardware. I know that after the reset, the cpu fetch the instruction from flash/rom, this is said as bootloader. But I don't...
  11. blueagate

    Help, does anyone has MIPS development board schematic?

    mips board schematics Hi, my friends, I can not open https://www.sveasoft.com/modules/phpBB2/index.php why?
  12. blueagate

    How to build a evaluation FPGA board with MIPS controller?

    MIPS Board Hi, my friends, does anybody have any docs/ shchematics/ tutorial on how to built an evaluation/ prototyping FPGA board with MIPS microcontroller? We have the soft code of MIPS, download to the FPGA. Thanks.
  13. blueagate

    Help, does anyone has MIPS development board schematic?

    mips development board I will develop a MIPS board, but I am a novice with MIPS, Does anyone upload some MIPS development board schem and doucument? Thanks
  14. blueagate

    [SOLVED] Anybody has the VHDL Code for Flash Interface

    flash vhdl interface AMD Flash Model Maybe helpful to you VHDL/Verilog Models for 3.0 V Simultaneous Read/Write Devices https://www.amd.com/us-en/FlashMemory/TechnicalResources/0,,37_1693_3047_9904,00.html
  15. blueagate

    Question about scan insert using Design Compiler

    design compiler how to compile with scan Hi, my friends I added the port scan_en at the top module, and I wrote the script: set_scan_configuration -style multiplexed_flip_flop crete_test_clock -period 100 -waveform {0 50} clk #clk is a port in the RTL code set_scan_signal test_scan_enable...
  16. blueagate

    How many decoupling capacitors should I use for VirtexII Pro

    Hi,honghongrong I remember that Xilinx provides an application note xapp158 "powering virtex fpga", you can find some advices in it, if you can find the similar application note about virtex II pro in xilinx web is better.
  17. blueagate

    Connecting Multiply FPGAs together

    I think choose the SSTL is better, many high speed devices such as DDR SDRM using SSTL standard. Using differential signal standard means double number wires have to be deal with in PCB design, adding difficulty.
  18. blueagate

    Question about scan insert using Design Compiler

    preliminary scanning ullman compiler design I want to inset scan from RTL code. The script I had written is here: analyze -f verilog top.v elaborate top some constrains here ... set_scan_configuration -style multiplexed_flip_flop crete_test_clock -period 100 -waveform {0 50} clk #clk is a...
  19. blueagate

    I want some DC scripts and RTL codes.

    Hi, xwcwc1234, DC have the define_name_rules for someone who want to configure the net name, I am the beginner, so I don't know how to write the script, but you can search define_name_rules in DC user guide.
  20. blueagate

    I want some DC scripts and RTL codes.

    Hi, arunragavan, I want the full tutorials about DC, so the more beginners can start DC from it. Thanks.

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