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Lets say Q0 Q1 is output of these DFFs
D0 and D1 is input of DFFs
D0=Q0 (XOR) Q1
Output of Machine lets say Z0 and Z1
Z0=Q0 (AND) Q1
Z1=Q0' (AND) Q1
Z0,Z1 Will be
They use sum [4:0] for a carry out bit. u can use sum [3:0] and a different carryout bit.
For a 2 bit full adder u have to have 4 half adder. so i feel a and b will use in another half adder. Isn't it.I m getting u correct.