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  1. A

    convolution of image in verilog

    can anyone please give me the verilog code for convolution of an image...or give me some guidence for implementing the convolution algorithm in verilog....
  2. A

    Question to image processing experts in FPGA???

    Hi FPGA experts i need a help in processing an image.....plz find the attachment of the image it is having some some white lines...here i have to count those white lines....how i can do this in FPGA.....already i processed the image using sobel edge detection but i didnt get exact edge detected...
  3. A

    verilog code for canny edge algorithm

    plz some one tell me is there any verilog code is available for canny edge detection algorithm.....already i have implemented the sobel edge detection bt it is giving expected result....so plz some help me in writing canny in verilog.....:sad:
  4. A

    doubt in using function

    can we call a function in ever posedge of clk..... for example always @ (posedge clk)begin a= function [b,c]; function[7:0]out; input b,c; out = b+c; endfunction end whether this possible.....
  5. A

    help in reading a large text file using verilog....

    thanks for yur reply i didnt understand wat u r trying culd u plz explain with simple example...
  6. A

    help in reading a large text file using verilog....

    I am having a large text file which contains only the pixel values of an image.....here i can able to read the pixels using $readmemh system task..... but the prolem is memory......am using only 1000 words of memory as below reg [31:0] Mem [0:999]; initial...
  7. A

    plz help me in this verilog code

    module readmemh_demo ( output reg lclk, output reg [31:0] pixels ); reg [31:0] Mem [0:20]; initial $readmemh("pixels.txt",Mem); reg[7:0] k; reg[7:0] i; initial begin $dumpfile("file.vcd"); $dumpvars; end initial begin lclk = 0; k = 0; pixels...
  8. A

    reading image data stored in text file using vhdl in xilinx

    Re: reading image data stored in text file using vhdl in xil hi guys the same i have do it in verilog....can someone help me out...
  9. A

    Explain me how would this be assigned

    how it will be assigned reg1<= #10 reg2 ; reg3 = # 10 reg4 ;
  10. A

    whether FPGA 's are having internal RAM?

    thaks a lot trickyDicky....
  11. A

    whether FPGA 's are having internal RAM?

    whether FPGA 's are having internal RAM....if it has means then plz some one tell me the internal RAM of EP2C35F672C6.....
  12. A

    doubt on sequential blocks

    Please some one let know can whether we can use blocking statements in sequential blocks....
  13. A

    How much clock do I need for this for loop in Verilog?

    for loop in verilog how much clock is required for the below for loop... always @ (posedge clk)begin for(index = 0;index < 10;index = index + 1)begin row1[index] <= #1 row2[index]; end end In simulation i see it is taking only clock....is it possible???
  14. A

    plz help me in this logic

    No....actually once the sequence is encountered after that we have to start from the next sequence to increase the count.....like 51,21,22,23,24,25,26,27,28,29,30....here i expect to see the counter as 2.
  15. A

    plz help me in this logic

    anybody plz tell me how to write program for the below logic... Am having array of a[2000] elements in that i have to increase a count if the numbers are continuously in order for five times like 1,2,3,4,5 for example a[0]=1,a[1]=2,a[2]=3,a[3]=4,a[4]=5, then i have to make a count.....if it is...
  16. A

    sequential code and combinational code in verilog

    Am new to verilog.......somebody can give me some example code for sequential verilog code and combinational verilog code plz explain me how both works in always posedge of clock.....
  17. A

    What is an easy way to multiply a binary number by 255?

    Re: Help Required! left shift by 8 times is the better way....
  18. A

    algorithm plz its urgent

    hi dilinx thanks for yur reply....could you plz explain me in detail or can you give the code as you mention
  19. A

    algorithm plz its urgent

    0 1 2 3 …….. ……. ………. 4031 4032 4033 4034 4035 …….. …….. …….. 8063 8064 8065 8066 8067 …….. …….. ……. 12095 12096 12097 12098 12099 …….. …….. …….. . . . consider the first 3x3 matrix from the above 0 1 2 4032 4033 4034 8064 8065 8066 matrix here the center location is 4033...
  20. A

    algorithm or logic for the attached document!!plz its urgent

    Actually the document is for image processing.Plz any one read it and tell me some solution.

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