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  1. azerm

    What is clock uncertainity and why does it happen?

    clock uncertainity clock skew is mainly delay in clock arrival between different points due to different clock network from clock source to those points. clock uncertainty is variation in clock period for one point, regardless of other points.
  2. azerm

    The technology library contains power information ?

    what do you mean about add this to your testbench? common power estimation tools use simulation results, ex. VCD file to do power estimation.
  3. azerm

    questions about Delay Chain

    in major digital std cell libs, there is some delay cell like DLYxx. look into the std cell list.
  4. azerm

    Difference between RTL and behavioral code

    RTL Vs Behavioral Behavioral codes may be synthesizable or non-synthesizable. If you want to use tools like behavioral compiler to automatic scheduling and resource allocation, the code must be written with behavioral coding style. I use in in some designs, the result is very interesting. But...
  5. azerm

    clock tree spec and buffer list

    during synthesis, you mut specify clock ports as ideal network with appropriate command (like set_drive 0), so synthesis tool does not insert any buffer for these ports.
  6. azerm

    What is common use file format for I/O pads in ASIC flow ?

    i/o asic pad Hi, PAD insertion in ASIC is very differenent with FPGA. There is no good way for automatic pad insertion, instead designer may put each PAD in the top level netlist same as other blocks. Also other PAD issues like power & ground, multi_supply pads, ESD rules, filler and breaker...
  7. azerm

    synthesis using cadence

    sdc_write_unambiguous_names Is this flow ok with BG?
  8. azerm

    VHDL vs Verilog which more popular?

    Each of VHDL or Verilog has its own advantages, and also it depends on softwares you use. For example in Cadence flow, Verilog is more useful. But there are some other selections like SystemC, or in the future, SystemVerilog. It seems that these languages have good growth in the professional...
  9. azerm

    $ynplify ASIC vs. Design C0mpiler

    I think if anyone wants to synthesis any real circuit he can do it with most synthesis tools. I myself have synthesized and also tape out with DC, S.ASIC and even Leo*nardo. (ASIC PROJECTS). All of them works well. But if you want to synthesis a design with more than 200k gates and with newer...
  10. azerm

    I need an FPGA Advantage 5.5 licence file if you can help me

    Hi, As i know, the latest version is 5.3, not 5.5. So if you need lic for 5.3, I can help you. PM me.

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