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I am new to signal processing and currently trying to understand the DCT concept.
There are mainly 2 conceptual questions I have:
1) the dct equation is given as:
Xk = summation (xn cos ....)
Which can be expanded as:
x0 = x0 cos (0) + x1 cos (..) + x2 ...
Anyone know about a good links to reset schemes. Especially looking for information on circuit reset schemes that contain FPGAs since the reset should be active until FPGAs are configured.
Some of the IO standards (e.g. CML) actually do not use CMOS transistors inside their IO buffers. Since most of the FPGAs are follow CMOS technology and they also support these IO standards, how are these actually supported?
Of course, the same question would apply even to ASICs also...
I was looking into datasheets of some analog and mixed signal ICs and they dont contain any jtag port. So is it generally the case that analog ICs are left out of jtag chain. Also, why not have a jtag port and include them since that would make board testing so much simpler?
Can anyone tell me how low speed clocks are derived in i2c or uart applications.
As I understand these cores typically operate at core frequencies which could be 50Mhz upwards. Specifically I have the following questions:
1) Does most of the cores (i2c core) operate at core frequency and...
what do divisions mean on a clock
I have couple of questions pertaining to clocks
1) why is it necessary that one uses analog logic like pll to do a clock division when it can be done using just flops
2) why fpga technology prohibits logic in the clock path e.g. to gate the clocks
I am going through a xilinx app note. The basic CAM that is shown is a
32X9 capacity. The total memory capacity used up to implement this is
16kb. I am wondering if the idea is to generate just a match or
no_match then just a 512 bit single bit memory array would do the job.
Where the array...
I am looking at a legacy design. The design accepts 2 clocks (of same frequency and from same source), one goes to core logic and other goes to SERDES block.
I am not sure why an indepdent clock is fed separately to SERDES while the same
core clock can be used. When I refered to design document...