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    Rivera Pro adding UVm libraries

    Hi, I am trying to simulate UVM methodology using rivera pro. I can compile the program using commandline alog -l uvm filename.sv . but I do not know how to add the uvm libraries to the GUI simulator. when i try to compile using HDE>simulate I get errors saying that the library is not found and...
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    problem when checking signal on rising edge

    hey guys. I am trying to simulate a processor on vhdl and here's my problem. I am having trouble when updating my PC. the sequential code for updating PC is given below As you can see I am trying to check for a data hazard stall and if it happens, the my PC_reg shouldnt update. but as seen...
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    Cadence standard cells

    Could anyone give me some info on standard cells in cadence? I would like to know the list of standard cells, then naming conventions etc? like when cadence converts the verilog module into a schematic entry, it picks the various modules based on the name right? where can i find all such info?
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    DRAM cell operation_ problem with the working

    So I have a DRAM cell simulated. I understand we are not to raise the word line when the column line is low since there is no need for that. But shouldn't the capacitor be discharging when the gate voltage is low? why is it at about 750mV when the gate voltage is low and the source is high?
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    deep trench capacitors in GPDK45nm

    Hi I am using GPDK45nm technology for my design. I am thinking of simulating a DRAM memory cell. But problem is i cannot find deep trench capacitors that gives about 30-50f F to store the charge. I am onl able to use the default mimcap which needs a very large area for the required cap. could...
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    question about advancements in DRAM

    https://www.emrl.de/imagesArticles/DRAM_Emulation_Fig2.jpg I was studying about DRAMs and was wondering whether the DDR2 ram and other types of DRAM still use the same cell design as the memory element(a transistor with a capacitor) or have DRAMs advanced beyond the primitive design. I have...
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    cannot attach gpdk045 technology to new library

    I have extrracted the gpdk045 library to my cadence installation and am able to do the schematic simulation properly without attaching the tech library. But to do virtuoso layout, we must attach the tech library to the project but I am not able to see an option for gpdk045 in the technology...
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    OPAMP temperature protection circuit

    Hi,I am laying out an OPAMP in cadence IC 615using AMI 16 tech and would like to implement a thermal protection circuit that will shut off the power to the transistor if the temperature rises above a preset value. Could anyone point me in the right direction?

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