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  1. S

    How to display characters on a vga console?

    Re: vga console thanx, but isnt there a simpler way? Added after 12 minutes: actually i dont know VHDL. could you help me understand how this was done in the link that you gave me
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    How to display characters on a vga console?

    Re: vga console thanx for your help. actually i am going to use the Picoblaze microcontroller to control the characters to be displayed on a VGA monitor. the Picoblaze microcontroller will get the character from the UART and then accordingly display it. im having some difficulty in figuring...
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    How to display characters on a vga console?

    vga console i have made a 640x480 VGA controller in verilog. as a test i generated red green and blue lines on a monitor. but now i want to display alphanumeric characters. i have some idea about using a character buffer and a font ROM. but can someone please tell me how i should do it?
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    can i unplug the vga cable while windows is running

    how to unplug vga cable actually they have the same ground. i have one power cable coming from the power outlet going into the CPU then from that i have given the power to the monitor. i remember that the two sockets on the power supply of the CPU are simply connected in parallel. so both have...
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    can i unplug the vga cable while windows is running

    monitor only turns on when unplug vga actually im designing a vga controller on an FPGA and for that i have to check the design again and again. for that i have to first disconnect from my dialup connection and then shut down my pc and then connect the monitor to the FPGA kit. i was just...
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    signed addition in verilog

    verilog addition im doing a project in which i need to add two signed numbers. how can i check for underflow and overflow? module stimulus; reg signed [7:0] a,b; wire signed [7:0] c; signed_adder my_adder(a,b,c); initial begin $monitor($time, " a = %d, b = %d, c = %d", a, b, c); end...
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    FPGA Kit : Xilinx Starter vs Altium LiveDesign

    okay i have decided to buy the altium live design evaluation kit. but when i contacted the local altium sales dealer he told me that there will be $50 for the freight. $50 is half the price of the kit itself!!!! are the freight expenditures same in other parts of the world. how much is it in...
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    FPGA Kit : Xilinx Starter vs Altium LiveDesign

    Re: FPGA Kit : Xilinx Starter vs @ltium LiveDesign thats because i dont know what they mean :D
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    FPGA Kit : Xilinx Starter vs Altium LiveDesign

    what difference does that make? the altium kit has Dual 256Kx16-bit FPGA configurable high-speed static RAM is that as good as the flash memory in the Nu horizons kit? can somebody please explain in a little detail
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    FPGA Kit : Xilinx Starter vs Altium LiveDesign

    okay, so even though not all the pins are usable on the altium kit, the IO capabilities of the altium kit is more than the nu horizons/digilent kit. and if you remove those 7-segs you get more IO pins. my second question was that where is the bit file downloaded on the altium kit. doesnt it...
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    FPGA Kit : Xilinx Starter vs Altium LiveDesign

    okay first of all, im sorry for posting in an old thread. but i was about to ask the very same question that checkmate asked. then i thought that i should search first. okay now my question is that GeneralMadDog said that the starter kit has Flash. doesnt the altium kit have Flash. and what...
  12. S

    Help me connect 25MHz clock to FPGA and then get 400Hz clock

    Re: clock problem im using ModelSim 5.4a but i have seen this practice in the book "Verilog HDL- Guide to Digital Design & Synthesis". i like it this way too but maybe its because im using an older version of modelsim, i get that error.
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    Help me connect 25MHz clock to FPGA and then get 400Hz clock

    Re: clock problem first of all, echo47, modelsim gives me an error that it is expecting ';' near "=". but anyway that was the most simplest code i saw during this hunt for the best clock dividing code. Sparc, the clock divider works purrrrfect! i have attatched the verilog codes for both...
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    Help me connect 25MHz clock to FPGA and then get 400Hz clock

    Re: clock problem yeah, a flip flop is edge triggered while a latch is triggered on the level and not the edge (rising or falling) https://www.allaboutcircuits.com/vol_6/chpt_7/5.html
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    can somebody help me understand this piece of code of an FIR

    Re: can somebody help me understand this piece of code of an Renjith you are my hero. now it becomes all clear to me. actually i didnt see this type of bit shifting before. i knew that it was concatenating bits but i didnt know that it was actually shifting the bits. Added after 1 hours 39...
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    can somebody help me understand this piece of code of an FIR

    module fir_srg (clk, x, y); //----> Interface input clk; input [3:0] x; output [3:0] y; reg [3:0] y; // Tapped delay line array of bytes reg [3:0] tap0, tap1, tap2, tap3; // For bit access use single vectors in Verilog always @(posedge clk) //----> Behavioral Style...
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    Help me connect 25MHz clock to FPGA and then get 400Hz clock

    Re: clock problem feel_on_on if you just scroll a few posts above you will find the description and the code of my project.
  18. S

    Help me connect 25MHz clock to FPGA and then get 400Hz clock

    Re: clock problem i have Xilinx ISE 6.2.01i and i get the same results as you got. i have also done the implementation, place and route and generated the programming file. but i dont want clk2 to be driven by an external clock. i want it to be driven from clk. for that i would need a clock...
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    Help me connect 25MHz clock to FPGA and then get 400Hz clock

    Re: clock problem Ehm Renjith can i get something in Verilog :D i have no knowledge of VHDL. Sparc thanx alot for your concern. i have attatched the test bench that i simulated in Modelsim. ill give you a brief overview of what i want to do. the whole system consists of a 4-bit UART at the...
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    Help me connect 25MHz clock to FPGA and then get 400Hz clock

    Re: clock problem Renjith can you give me sample code for the 16-bit counter? and one thing more. i entered my code in Xilinx ISE but the synthesis report tells me that there is no clock signal in my design. do i have to use some specific keywords for the clock signal. i have tried reading the...

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