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Re: verilog first code
no no it is right
all the problem that i didnot make project:D:D:D:D
excuse me this my first project
by the way this sentence is right
and thanks for your modification it is very suitable not large as i write and thanks also for the illustrate of the difference between...
i'm new in verilog and need test semple project using logsim
this is the code
module counter (clk, reset, enable, count);
input clk, reset, enable;
wire clk, reset, enable;