Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. M

    Verilog code error: unable to determine top module

    Re: verilog first code no no it is right all the problem that i didnot make project:D:D:D:D excuse me this my first project by the way this sentence is right and thanks for your modification it is very suitable not large as i write and thanks also for the illustrate of the difference between...
  2. M

    Verilog code error: unable to determine top module

    salam alikom hello i'm new in verilog and need test semple project using logsim this is the code ///////////////////////////////////////////////////////////////////////////// //counter project module counter (clk, reset, enable, count); input clk, reset, enable; wire clk, reset, enable; output...

Part and Inventory Search