Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
vhdl clock divider
i am a beginner in ASIC. In VHDL i was able to design divide by 3 or divide by 5 circuits using FSM.is it possible to get an 2/3 divider circuit ??. actually the problem is to get 33.33 MHZ from an 50 MHZ source.
kindly suggest me some technique to achieve it...