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    how to get an 2/3 clock divider using VHDL

    vhdl clock divider hai friends i am a beginner in ASIC. In VHDL i was able to design divide by 3 or divide by 5 circuits using FSM.is it possible to get an 2/3 divider circuit ??. actually the problem is to get 33.33 MHZ from an 50 MHZ source. kindly suggest me some technique to achieve it...

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