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  1. N

    APB read - do I need to consider penable

    Hi For APB read transaction , if read operation , do I need to consider penable =1 to output the data on bus ? Thnx niraj
  2. N

    clock frequency for below scenerio

    Its like when rising edge of '1' bit data I am shifting 1 for 8 times and falling edge of '1' data bit I am shifting 0 here . So in total 16 cycles output of 8 bit vector .
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    clock frequency for below scenerio

    Basically a 1 bit is divided into 16cycles of 8 bit vector . So want to know the clock for this 8 bit vector generated ? Eg if 1 bit generated in Tbit clock then is (Tbit clock/16) is the clock of 8 bit vector generated ? let me know an I making sense now Thanks
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    clock frequency for below scenerio

    Hi , I am generating one bit data (Manchester code ) at Tclock period. This 1 bit data is sent in 16 cycles in 8 parallel bit format . Basically a shifting 1 for rising edge and 0 for falling edge eg . 1000000 1100000 11100000 ...................... 10000000 11100000 what should be the...
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    Manchester Encoder_Decoder

    HI, I need to code Manchester encoder - decoder . I am very new to this . Can any one provide the Manchester encoder and decoder code in VHDL please . Thanks in advance ! Niraj
  6. N

    which EDA tools used to write behavioral models for -PLL ?

    Yes I want to have model out of analog block . So in this case does all the behavioral model for analog blocks are hand coded ones ? Thanks for your reply ,
  7. N

    which EDA tools used to write behavioral models for -PLL ?

    Hi , Could you pl anyone let me know the best method to extract the behavioral model (verilog)for analog components like PLL or any analog component . Usually we see for Simulation purpose we hand-code at abstract level . however these models are proven to manual error , and hence live with...
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    Increasing Frq of operation

    For the same target library , Its been asked to make the core work from 100MHz to max frequency of 180MHz . So would like to know different ways of improving the performance. Thanks
  9. N

    Elastic buffer - RTL coding

    Hi , I need some good documents about implementation of Elastic buffer / 8b/10b encoder - decoder . It will be great if you could point me to relevant stuffs of these topics. Thanks in advance , Niraj
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    Positive skew and negative skew

    What is positive skew and negative skew means ? How they effect the Fmax ? Thanks , Niraj
  11. N

    Looking for clock divider circuits which get 33 MHz clock from 50Mhz input

    could anyone please specify the digital diagram to derive the clock of 33MHz from 50MHz input. Basically would like to know clock divider circuit for this . Thanks , Niraj
  12. N

    Increasing Frq of operation

    Hello there, consider a design which works for certain frequency of ex 100 Mhz and I have been asked to target this to 200MHz . From design/coding perspective would like to know best ways to increase the performance of speed of operation in terms of architecture , RTL coding apart from...
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    to increase the speed of Design

    Thanks for your reply. Yes true that flop needs to latch on edge of clock , so do current philosophy of flop. Also we can construct a dual edge flop , wherein flop latches data on both edges on clock ,yes it tedious process . I have got few info on these , further links helps .
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    to increase the speed of Design

    Hi Can we design a flop to work on both edges of clock ? In this scenario how do we takecare of timing and metastability issues ? Pls brainstorm your points . Also if you have any paper or link pls do point. It really helps me . Thanks in advance

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