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Basically a 1 bit is divided into 16cycles of 8 bit vector . So want to know the clock for this 8 bit vector generated ?
Eg if 1 bit generated in Tbit clock
then is (Tbit clock/16) is the clock of 8 bit vector generated ?
let me know an I making sense now
I am generating one bit data (Manchester code ) at Tclock period.
This 1 bit data is sent in 16 cycles in 8 parallel bit format . Basically a shifting 1 for rising edge and 0 for falling edge
eg . 1000000 1100000 11100000 ...................... 10000000 11100000
what should be the...
Could you pl anyone let me know the best method to extract the behavioral model (verilog)for analog components like PLL or any analog component . Usually we see for Simulation purpose we hand-code at abstract level . however these models are proven to manual error , and hence live with...
consider a design which works for certain frequency of ex 100 Mhz and I have been asked to target this to 200MHz . From design/coding perspective would like to know best ways to increase the performance of speed of operation in terms of architecture , RTL coding apart from...
Thanks for your reply.
Yes true that flop needs to latch on edge of clock , so do current philosophy of flop. Also we can construct a dual edge flop , wherein flop latches data on both edges on clock ,yes it tedious process .
I have got few info on these , further links helps .
Can we design a flop to work on both edges of clock ? In this scenario how do we takecare of timing and metastability issues ?
Pls brainstorm your points .
Also if you have any paper or link pls do point. It really helps me .
Thanks in advance