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  1. C

    Need a solution for Vin 1.8 to 12V , and vout~4.2V

    Hi ~ thanks ~! but i don't need a boost converter My project need something like buck/boost converter
  2. C

    Need a solution for Vin 1.8 to 12V , and vout~4.2V

    I have a power system need to design. It input voltage down to 1.8V and up to 12V; DC but often varies with time. Output Voltage is near 4.2V, Iout~600mA I search for TI; they have a buck/boost converter TPS55065-Q1. But it is very complicated than I needed. Has there other simple method to do...
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    Question of razavi's book (chapter 13 mismatch)

    Hi The equations (13.57)~(13.59) of razavi’s book at pp. 464 The result is that mismatch is inversely proportion to (n)^1/2. How to derive from eq 13.57 to eq 13.59? Thanks ~ !!
  4. C

    error amp of current mode buck converter

    buck converter current mode Hi ~~ The system bandwidth of buck converter often set : 1/10*clock Frequency . But the error amp spec only identifies Gm Av. How about the bandwidth , slew rate ?? Do we need a very fast slew rate of error amp? Or if slew rate too fast ,the system intends to...
  5. C

    nwell resistor junction leakage ?

    junction leakage Hi ~! If i have a resistor formed by nwell/P-sub structure, what is the junction leakage current about this resistor ? I have to know it because i have a very small current near 50nA need to pass a large nwell resistor about 3um*3300um. Thanks ~ !!!
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    question about psrr simulation

    psrr simulation Hi ~ i have an LDO regulator. and i simulate it psrr. i found it crossover 0db at about 90kHz (max +14dB). but if i use a 10mV 90kHz sin wave , the output have only 6mV sin wave , equal -4.4dB. what result is meaningful ?
  7. C

    model parameter of nmos drain to substrate leakage current ?

    Hi ~ Is any one know the parameter of nmos drain to sub reverse current (or say pn junction leakage current) in spice level 49 model ? Thanks ~ !
  8. C

    mos corner question - is the sf and fs corner possible ?

    mos coner we often say mos has tt ss ff sf fs corners. the s corner due to think tox and f corner refer to thin tox process, then vth will be larger or smaller. The oxide of pmos and nmos are processed in the same time. So the sf and fs corner is possible?? thanks ~ !!
  9. C

    Issues with loop stability of an LDO

    Re: Loop stability Hi I don't think the stability analysis is right. The phase up but the magnitude is still roll off, and the phase go up more than 90 degree, it is so wired.......because no inductor in here.. Where the stb probe you added ? ?
  10. C

    reference for low power constant current biasing circuit ?

    Hi ~~ Dose anybody have papers or any related book for very low power (supply current near nano A) constant current biasing circuit ? thanks !
  11. C

    Finding bandwidth using PAC

    Hi Could you please specify more clearly? The PXF analysis is almost the same as XF analysis. You can plot gain diagram (in dB) , and where the frequency of DCgain(max)-3dB is your BW.
  12. C

    constant current vdsat values of PMOS and NMOS

    mosfet model vdsat The Vds ≥ Vgs-Vth if MOSFET operate in saturation region. You should choose a proper operation point, by doing that you need to specify Vgs voltage. So the Vdsat = Vgs-Vth, this is the small vds vaule for MOSFET operating in saturation region. If vdsat is too large, the...
  13. C

    Question about simulation ICMR (input common mode range)

    icmr input common mode range Hi ~~ If I have a two stage single ended differential amp, and the input is rail to rail (has NMOS & PMOS as input stage), but output is cascode configuration (two nmos cascode & two pmos cascode). When simulation ICMR we often use unit gain configuration, connect...
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    solutions for Thomas H Lee

    I think you can search it using "EMULE"......
  15. C

    opamp simulation question (Vos & PSRR & CMRR)

    psrr simulation for operational amplifier hi LvW ~ The result of curve_cr.png is Vin & Vip all tied to ground and sweep a small voltage at Vip. I so curious why two inputs are zero voltage? the input transistors are all cut off.... This is the biggest point i can't understand .........! The...
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    opamp simulation question (Vos & PSRR & CMRR)

    simulating psrr in op-amp LvW : Thanks for your reply ~!! (i saw the message in designers-guide):D The testbench from cadence is not correct here. Because this is used to measure fully differential amp and including some verilog a code, so forget it. Yes my opamp is just only a classical...
  17. C

    opamp simulation question (Vos & PSRR & CMRR)

    opamp offset simulation thanks LvW How do you thinks this methody? It come from cadence white paper
  18. C

    opamp simulation question (Vos & PSRR & CMRR)

    free op amp simulator thanks for your reply the attached file is my opa & simulation result. i tied vin to gnd (vin DC=0) , and vip DC=0 sweep vip : -100mV to +100mV What is my Vos ? Is the two curve cross point? or other? thanks a lot ~!
  19. C

    opamp simulation question (Vos & PSRR & CMRR)

    psrr operational amplifier thanks you for your reply But as i said , if the input and output is not rail to rail, how to modify this simulation steps ? Added after 2 minutes: So is the Vos not a certain value ? it depend on input voltage? is it ? thanks !
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    opamp simulation question (Vos & PSRR & CMRR)

    cmrr op amp Hi~~~~ If i have a single ended opamp, i want to simulation it offset voltage. I often see the simulation step is that Vin+ & Vin- tied to ground and measure output voltage, the output voltage/Gain is the Vos. But when input of opamp is NMOS transistor and single voltage supply, it...

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