Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. V

    FPGA Implementation Verification

    I already have a top module which is the oc8051_top.. okay I will try instantiating the ram into it... And as you told me about the .ucf and .xcf... Am already done with all of that... I just wanted to create the Block Memory as a Post Synthesis process!!
  2. V

    FPGA Implementation Verification

    No I still haven't instantiated it... i have the .coe file with me... i tried generating a blocked memory by choosing this .coe as an Init File... Now I have a blk_mem_gen (.xco file) that is added in the ISE source list... What I did till now is right? If so what should I do next?
  3. V

    FPGA Implementation Verification

    Thanks for your reply!! As far as what I understood, RAM can be initialized through .coe file... But I have difficulty with instantiation process... Any help with that??
  4. V

    FPGA Implementation Verification

    hello... am supposed to implement a 8051 open core (verilog programming) into a Xilinx spartan 3e (xcs3500e) board and verify the implementation with led blink program.. i have implemented the core into the fpga successfully though ISE and iMPACT... My question is how can I load the blink...
  5. V

    [MOVED] Intel 8051 Verilog Code

    Hello. I'm new to this programming world and I need your help. I'm supposed to implement an Intel 8051 core in FPGA(Spartan 3E). So I checked the following websites: 1. Oreganosystems website. They offer codes only in VHDL. 2. Checked opencores.org. It includes verilog code here...

Part and Inventory Search

Top