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  1. S

    min skew check

    Why do we have a check for min skew? What does this help avoid? Thanks!
  2. S

    source synchronous bus and hold violation

    When we send data and clk using source synchronous fashion, and if we assume that skew is ~0, the receiver could have setup and hold violations right? Why are we more concerned about hold violations with source synchronous bus? Isn't setup violation just as probable as hold violation?
  3. S

    Reset Value using a parameter

    Let's say that I have a data[WIDTH-1:0]. I want to use a parameter in RTL to provide the reset value for this data. parameter RESET_VALUE = 5; logic [WIDTH-1:0] data; always_ff @(posedge clk) if (~reset) data <= WIDTH'd (RESET_VALUE); else .... How do I make this work syntax...
  4. S

    Using generate and for loop to index signal name

    Say I have inputs as follows: input in0; input in1; input in2; input in3; ... and what I want to do in generate for loop is something like this. b[0] = in0; b[1] = in1; b[2] = in2; ... and so on. The problem is I cant index the inputs using the variable 'i' in the generate for loop. How can...
  5. S

    default statement in case

    If i put this statement (state_nxt = state;) at the very top of the always_comb, the default statement in 'case' is not required for it to not synthesize into a latch. Is this correct? Would you still put the default statement for simulation purposes and why? always_comb begin state_nxt =...
  6. S

    Beginning and end of a time step

    Non-blocking assignment evaluates the RHS expression at the beginning of a time step and schedules the LHS update to take place at the end of the time step. Let's say we have always_ff @(posedge clk) c <= a | b; If we have a non-blocking assignment inside a always_ff block, does the...
  7. S

    Optimizing case statement with large input

    case (input[9:0]) 0: ... 1: ... 2: ... ... 1023: .. default: ... endcase Let's say that there is a 10 bit input and have 1024 possible case statements. If I were to write the case statements in such a way, input == 0 will have the highest priority, and so on. 1. If this the...
  8. S

    if/else vs. if/if in combo logic

    This code (which has if/else) will take the comparison of "in == a" as higher priority. always_comb begin out = 0; if (in == a) out = y; else if (in == b) out = z; end However, this code below (which has if, if) also imply the same priority. Are they functionally the same? Will the two...
  9. S

    blocking assignment in always_comb

    1. Are these two code functionally equivalent? 2. Will they synthesize into the same hardware? always_comb out = 0; out = (sel[0]) ? in[0] : out; out = (sel[1]) ? in[1] : out; assign out = sel[1] ? in[1] : sel[0] ? in[0] : 0;
  10. S

    recovery time of sync reset vs. async reset

    1. for sync reset, we have to time assertion and deassertion of the reset? But for async reset, we only have to time deassertion of the reset right? 2. I'm reading that one of the advantage for sync reset is that it will meet reset recovery time because its synchronous. Don't we have to meet...
  11. S

    Always @ flop holding value when else is not specified

    Let's say we have a flop declared like this. When we = 0, it is assumed that ram will hold its value, and when we = 1, the value will update to din. If we don't specify what happens with else, why does this construct implicitly loop the flop output into the input of the mux even though we...
  12. S

    How to synchronize two LFSR between PRBS generator and checker

    PRBS Generator -----> DUT -----> PRBS Checker If we have the same LFSR with the same seed in the generator and the checker, at some point, the two LFSR will start generating the same sequence. We want to match the output from the generator to the checker through the DUT. since the DUT will have...
  13. S

    priority on two asynch triggered events

    If we write verilog like this with async set/reset, does the synthesis tool use FF with this priority? (reset has higher priority than enable) always @(posedge clk or posedge reset or posedge enable) begin if (reset) out <= 1'b0; else if (enable) out <= 1'b1; else...
  14. S

    Clock cells adding jitter to clock

    do clock cells on the clock path add to jitter? For every clock cell we add on the clock path, we are adding random latency through it. And different clocks on different clock path could have very different jitter? 1. won't this make the jitter on the clock much worse? 2. does this also add...
  15. S

    minimum depth for data streaming through async fifo

    Suppose read/write clk frequencies are EQUAL but are async. What is the minimum depth of async fifo required to stream data through it and why? Thanks!
  16. S

    Reverse case statement with multiple matches

    case(1′b1) // takes 1′b1 and compares with underlying variables var_1: <some operation> // checks if var_1==1′b1 var_2: <some operation> // checks if var_2==1′b1 default: <default operation> //if none of variable is 1′b1 then execute default endcase 1. In such an example, what happens when both...
  17. S

    AI Accelerators hardware for AI applications

    I just wanted to get some idea on what kind of hardware the AI accelerators are made up of. Does it have a bunch of cores optimized for multiplication and add? What kind of operation will it need to do for AI applications? Thanks!
  18. S

    latches in timing (do latches get timed as destination or as combo logic)

    If the tool sees a latch in the timing path, does it try to meet setup/hold time to the latch or does it assume it is transparent and find the destination flop? It needs to meet both timing requirements as destination and as combo logic right? How does this work?
  19. S

    Up counter or down counter

    between an 8 bit up counter and a down counter, which synthesizes into smaller hardware?
  20. S

    how does insertion delay affect timing

    Lets say the skew is 0. Does the insertion affect the timing at all in this case? I would assume it would affect the external signals, but what about timing on internal flop to another internal flop?

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