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  1. J

    i m fresher- plz guide me

    Hi, There are free tools for Analog Layout Design. They are MicroWind and Magic. These tools come with the document "how to draw a inverter". Rgds, JK
  2. J

    startup companies in vlsi

    There are many VLSI startups in Chennai www.atmel.com www.atheros.com www.aceltech.com www.xambala.com www.mbitwireless.com
  3. J

    is there any book useful aboat pnr?

    naveed shervani is the good book to start
  4. J

    Using perl tk to generate a Hierarchy Browser

    perl hierarchy browser Hi , Have any one used Perl TK to generate a Hierarchy Browser . I am trying to do one . If you have some info can u pls share it with me .. -Jay
  5. J

    ESD and IO circuit design

    Does anybody has soft copy of book on ESD and IO circuit design.
  6. J

    How to design Sigma Delta ADC?

    xilinx comparator delta sigma me too doin the project in sigma delta ADC design. let me say what steps i followed to bring out the chip First i took the required spec , mine was 0.35u CMOS 70Mhz continous time bandpass ADC . There is basically a filter which is the major part of the design...
  7. J

    The advantages of using MAGMA for ASIC

    Re: ASIC with MAGMA can any one suggest any free tool for power analysis
  8. J

    How to write a script for synthesis

    can anyone tell how to write synthesis script for MAGMA
  9. J

    What is the best way to reduce power for low power ASIC?

    Re: LOW POWER ASIC Is there any free tool for power analysis can anyone help me
  10. J

    Architecture level Optimization for ASIC

    Can anyone tell the best architectures for the basic elements like adder , accumulator, multiplier. i found that wallace tree multiplier is the best multiplier architecture anyone can comment on it
  11. J

    Static Timing Analysis

    set_clock_transition can anyone tell me how to select set up time, hold time , rise time , fall time. is it depend on the frequency of the design or the technology library do we need to give transition time for the output pins also advance thanks waiting for reply
  12. J

    What is the best way to reduce power for low power ASIC?

    LOW POWER ASIC Does anyone working on low power, If yes which is the best way to reduce power is by doing architectural analysis or gate level analysis
  13. J

    powermill, power compiler & prime power

    does any power optimization tool is free downloadable can anyone know tell me
  14. J

    Looking for a sample ASIC design flow

    Sample ASIC Design flow can anyone tell me good website which provide me sample netlist to asic design flow, so that i can do only P & R, is there any sample verification modules , which talks abt verification plan , test plan , test cases waiting for good reply
  15. J

    The advantages of using MAGMA for ASIC

    ASIC with MAGMA does anyone tell how far this tool is better than other tools like cadence any synopsys. can anyone tell wht is best feature in magma and why it is advantageous than others how far it cope up with low power vlsi
  16. J


    formal verification is signoff once you get your netlist and have run few gate level simulations. Now wht is formal verification? Basically formal verification is parted down into two a) Model Checking b) Equivalence checking It is nothing else but checking the transformation ...i.e...
  17. J

    How to design and implement a GPS receiver?

    bfr91 receiver wht information u need did u need abt communication related gps or asic related gps
  18. J

    Implementation using DSP and FPGA in a CDMA project

    Re: CDMA have anyone working in cdma asic chip design if yes which architecture is best for low power
  19. J

    Looking for GPS manufacturers or dealers in India

    Re: GPS u can do google search and u can get lot of information wht part r u working RF / FPGA / Processor
  20. J

    question on magma synthesis??

    u try to instantiate correct technology library cells or try to add component from the library u have

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