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xilinx comparator delta sigma
me too doin the project in sigma delta ADC design.
let me say what steps i followed to bring out the chip
First i took the required spec ,
mine was 0.35u CMOS 70Mhz continous time bandpass ADC .
There is basically a filter which is the major part of the design...
can anyone tell me how to select set up time, hold time , rise time , fall time.
is it depend on the frequency of the design or the technology library
do we need to give transition time for the output pins also
waiting for reply
Sample ASIC Design flow
can anyone tell me good website which provide me sample netlist to asic design flow, so that i can do only P & R, is there any sample verification modules , which talks abt verification plan , test plan , test cases
waiting for good reply
ASIC with MAGMA
does anyone tell how far this tool is better than other tools like cadence any synopsys.
can anyone tell wht is best feature in magma
and why it is advantageous than others
how far it cope up with low power vlsi
formal verification is signoff once you get your netlist and have run few gate level simulations.
Now wht is formal verification?
Basically formal verification is parted down into two
a) Model Checking
b) Equivalence checking
It is nothing else but checking the transformation ...i.e...