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    Model Sim Error:Assuming recursive instantiation

    vsim-3036 Hi guys, I'm getting this error in Modelsim when I try to simulate my codes: # ** Error: (vsim-3036) Instantiation depth of '/ldpc_encoder2' is 81. Assuming recursive instantiation. # Region: /ldpc_encoder2 # ** Error: (vsim-3036) Instantiation depth of...
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    WARNING:Xst:1290 - Hierarchical block <d_ff0> is uncon

    xst:1290 - hierarchical block Hi guys, I'm getting the below error during Synthesize-XST in Webpack 8.1i. Can anyone tell me what to do. There is no syntax error in my program!!! WARNING:Xst:1290 - Hierarchical block <d_ff0> is unconnected in block <encoder> here is my...
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    problem in Test Bench Waveform(TBW) in Xilinx Webpack 8.1i

    Hi guys, I've a problem while working with TBW in Webpack 8.1i. here are my codes: module encoder(mesg,clk,cwd); input [15:0]mesg; input clk; output [15:0]cwd; wire [15:0]q; // o/p from the buffer i.e D_FF wire [15:0]s_p;// o/p from the serial to parallel shifter DFF...
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    Memory Intialization in Xilinx ISE 8.1i Webpack

    Hi friends, I've a 16x16 matrix which i need to store in a memory and use the values for my calculation.I'm coding it in Verilog. I'm not sure how to initialize the memory and store it. The Webpack has tools like Core generator and lot other stuffs. Can anyone tell which one to...
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    Pre-Silicon Validation

    Hi friends, I need to know what excatly does a pre-silicon validation engineer does? what are the toos and methodologies that the engg needs to know? does JTAG falls under pre-silcon validation? please help asap thanks
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    numerical examples for LDPC decoder?

    ldpc examples hi, Is there any paper which gives the numerical solution for the iterations carried in the LDPC decoder i.e. like atleast for 2 iterations, the value of check to bit and bit to check nodes are calculated. sriram
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    Rules for creating LDPC H matrices

    hi, can anyone tell me the ways or creating sparse Parity matrix for my LDPC encoder. What are the rules of creating a H matrix. thanks
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    Can you define 2 modules on the same page while coding in Modelsim?

    hi, is it possible to define 2 modules in the same page while coding in Modelsim.
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    Verilog simulation error: instantiation of alu_operation failed

    hi, I'm trying to simulate a simple verilog program(alu operation).i can compile the module n test bench. but when i wanted to simulate it, i'm getting an error Loading work.test_bench_alu_operation # ** Error: (vsim-3033) C:/Modeltech_xe_starter/my examples/test_bench_alu_operation.v(6)...
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    Question about LDPC, error correcting codes

    hi friends, I'm doing my masters in Elect engg.My final proj is on simulation, synthesis and implementation of LDPC codes. when i went through some of the technical papers, they were spking abt various functional evaluation methods (like CORDIC, polynomial approximation, look up...
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    How to infer flip-flops from CLBs?

    hi I am trying to infer 128 bit register in spartan-3 FPGA. when i implement the design i get error during the mapping stage " The design is too large for the given device and package." it is mapping the flipflops to iobs and the package xc3s200 doesnt have enough iobs . is there any way i...
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    Ideas for final year topic in VLSI and networking area

    need a project title hi freinds, I'm currently doing my MS in EE engg.I've to decide my final project for my degree.I'm planning to do something in VLSI+networking.I was going through the differnt hardware architectures of intel,cisco,IBM network processor.But i'm stll vague in...

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