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    Creating module in allegro

    Hi all, Can anyone explain the step by step procedure in creating module for design reuse. I have four same power supply in my board So draw schematic of power supply and linked it to heirarchial block . Then i created the netlist and opened it in allegro and routed pcb. How can i create...
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    SDRAM routing guidelines

    Hi Kapil , Thanks for that, But i have a few doubts. What should be the minimum length of the data signals and address signals? Is the clock length greater than data sig? Do i need to route address ,data and control sig in same length. Can u post the placement of DDR in any of your pcbs...
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    SDRAM routing guidelines

    Hi Kapil, Datasheet is attached.
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    SDRAM routing guidelines

    Hi Kapil, I am using Cadence allegro. Memory chip am using is SDRAM not DDR .It doesnt have the data strobe, there's only data and mask signals.There are 4 SDRAM chips.
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    SDRAM routing guidelines

    Hi marce, Datasheet doesnt specifies anything about routing guidelines. I have done pcb's with DDR SDRAMs . I think SDRAM s are not that critical as DDRs. Do i need to follow the same guidelines for DDR.
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    SDRAM routing guidelines

    Hi all, I am working with a pcb with 4 SDRAM chips (TSSOP package) .Data, address ,control and and clock are connected to all the 4 SDRAM chips. What is the routing strategy that i should follow.What should be the length of the signals. Thanks in advance
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    Schematic Design in Concept HDL

    Hi all I have been drawing schematics in Capture CIS for past few years. Now we have switched to Design entry HDL, Is there any tutorial for studying this.am new to this tool Can anyone help me Thanx in advance pcb 87
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    Auto routing in allegro

    Hello all, I have been using allegro 16.0 still havent tried auto routing in any pcb's Can anyone guide me in auto routing Would like to know about spectra too What is the difference between spectra and allegro pcb editor
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    Auto routing in Allegro16.0

    Hi all Can anyone tell me about auto routing features in allegro 16.0 ---------- Post added at 12:11 ---------- Previous post was at 12:06 ---------- How to set a constraint for a particular region...am working on a 10 layer board.using a 500+ pin BGA.created a region and set constraints for...
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    Auto routing in Allegro16.0

    How to use this script in auto routing
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    Merging of two PCB's in allegro.

    Can you please explain the procedure.. How should we draw the schematic then ? How merge it in allegro...
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    Merging of two PCB's in allegro.

    allegro merge Hii all.... Is there any option of merging two PCB's in allegro. ie two PCB's in same .brd file. If anyone knows please reply.
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    captire CIS to allegro 16.0 exporting error

    allegro gnd no-rat Hi all, I have drawn a schematic in capture CIS While importing it to allegro rats net for the net gnd is not showing. what may be the reason for this? Added after 1 hours 21 minutes: Added after 1 minutes: Hi , Found the solution for that. In the .brd file...
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    PCB Layout Considerations

    pcb layout considerations Hii Really helpful :-) Keep it update
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    Question about schematic symbols for ICs in Orcad Capture

    Re: Schematic Symbol Oh..sorry for that i'm using Orcad capture
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    Question about schematic symbols for ICs in Orcad Capture

    Hi all, I have a doubt regrading the schematic library. I created some schematic symbols for IC but they are to be created as a single part. So to combine them to a single part, I created a new part (heterogeneous) in the library and saved it. Then opened those single parts and copied them to...
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    How to design footprints in Allegro tool?

    allegro tool Hii reema, I have already posted a tutorial for allegrov14.2 pls check this link hopes this will help u
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    Length matching the DQS signal with clock signal in DDR2

    relation between dqs and clock in ddr2 I am using DDR2 DIMM.
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    Length matching the DQS signal with clock signal in DDR2

    routing lanes ddr2 In my design, according to the guidelines clock length is between 2 inch and 7 inch. and i routed all the colock signals as differntial pairs in 80mm length. I think there is no need to match the length of the clock signals and the DQS and DQM.. these are routed with...

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