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Can anyone explain the step by step procedure in creating module for design reuse.
I have four same power supply in my board
So draw schematic of power supply and linked it to heirarchial block .
Then i created the netlist and opened it in allegro and routed pcb.
How can i create...
Hi Kapil ,
Thanks for that, But i have a few doubts.
What should be the minimum length of the data signals and address signals?
Is the clock length greater than data sig?
Do i need to route address ,data and control sig in same length.
Can u post the placement of DDR in any of your pcbs...
Datasheet doesnt specifies anything about routing guidelines. I have done pcb's with DDR SDRAMs . I think SDRAM s are not that critical as DDRs. Do i need to follow the same guidelines for DDR.
I am working with a pcb with 4 SDRAM chips (TSSOP package) .Data, address ,control and and clock are connected to all the 4 SDRAM chips. What is the routing strategy that i should follow.What should be the length of the signals.
Thanks in advance
I have been drawing schematics in Capture CIS for past few years.
Now we have switched to Design entry HDL,
Is there any tutorial for studying this.am new to this tool
Can anyone help me
Thanx in advance
I have been using allegro 16.0 still havent tried auto routing in any pcb's
Can anyone guide me in auto routing
Would like to know about spectra too
What is the difference between spectra and allegro pcb editor
Can anyone tell me about auto routing features in allegro 16.0
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How to set a constraint for a particular region...am working on a 10 layer board.using a 500+ pin BGA.created a region and set constraints for...
allegro gnd no-rat
I have drawn a schematic in capture CIS
While importing it to allegro rats net for the net gnd is not showing.
what may be the reason for this?
Added after 1 hours 21 minutes:
Added after 1 minutes:
Found the solution for that.
In the .brd file...
I have a doubt regrading the schematic library.
I created some schematic symbols for IC
but they are to be created as a single part.
So to combine them to a single part,
I created a new part (heterogeneous) in the library and saved it.
Then opened those single parts and copied them to...
routing lanes ddr2
In my design, according to the guidelines clock length is between 2 inch and 7 inch.
and i routed all the colock signals as differntial pairs in 80mm length.
I think there is no need to match the length of the clock signals and the DQS and DQM..
these are routed with...