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    Don't care value during simulation

    Hi, What happens to "X" - don't care values during simulation? To understand what I'm saying here's an example: in a testbench there's the following statement: we = 1'hx; then, lines after there's the following test: if (we) // do something// (there's no else branch). What's the result of...
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    Analog and digital switches/ maximum input signal frequency

    Hi, Two beginner's questions: 1. What is the differences between an analog IC and a digital IC switch? 2. How can I find the maximum frequency for the input signal of a switch? I looked through the datasheet of a switch and I couldn't find a parameter that can tell me this. I want to use a...
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    [SOLVED] pull up value on signal that has driver

    Hi, I see that there are a lot of schematics where there are pullups on pins that also have a driver. Can you do this with any signals (i usually see it on reset signals)? How weak has the pullup so the driver can still make the signal 0? Thanks
  4. S

    [SOLVED] DC/DC converter input current

    Hi, Newbie's question, I was looking at the following DC/DC converter's datasheet: https://www.murata-ps.com/data/power/uwr15wa-series.pdf and I see that there is a parameter called Iin. I'm guessing that this is the maximum input current for the device, right? Why is this dependent on the...
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    Register read/write violate access

    Hi, In my code I have a register that is written with data read from SPI (register is 32bit and loaded after all the 32 bits have been read from SPI in a temp register). On the other side the register is read by the wishbone interface. My question is: do I have to worry that the data can be...
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    input never used error, although it is used

    Hi, I have the following code: always @(posedge clk) begin if (!rst_n) begin push_button_sts_d1 <= 1'b0; push_button_sts_d2 <= 1'b0; push_button_sts_d3 <= 1'b0; pb3_rst_d1 <= 1'b0; pb3_rst_d2 <= 1'b0; pb3_rst_d3 <= 1'b0; pb1_rst_d1 <=...
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    Question about the code for register file access

    Hi, A newbie's question, in the following code: module reg_file ( input wire clk, input wire wr_en, input wire [1:0] w_addr, r_addr, input wire [7:O] w_data, output wire [7:Ol r_data ) reg [7:Ol array_reg [2**1:0] ; always @(posedge clk) if (wr_en) array_reg [w_addrl <= w_data; assign...
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    access GPIO. Southbridge's registers

    Hi, I'm trying to access the GPIO pins on a motherboard under linux, 2.6.28 kernel. I read that if I have the sysfs support for the kernel (which I do :D) all I have to do is enable the respectiv pin using:echo N > /sys/class/gpio/export and I would get a gpioN directory, but I always get...
  9. S

    access GPIO. Southbridge's registers

    Hi, I'm trying to access the GPIO pins on a motherboard under linux, 2.6.28 kernel. I read that if I have the sysfs support for the kernel (which I do :D) all I have to do is enable the respectiv pin using: echo N > /sys/class/gpio/export and I would get a gpioN directory, but I always get...
  10. S

    PCI Express Interfacing

    Hi, Sorry if I'm posting a little bit out of topic here but I'm kinda confused. I read about the PCIe protocol, I read the Xilinx documentation about their PCIe EP and I have a quesstion: I understand that the CPU, through the RC, controls the transfer (issuing a read or write command) but how...
  11. S

    PCI Express Interfacing

    Hi, Sorry if I'm posting a little bit out of topic here but I'm kinda confused. I read about the PCIe protocol, I read the Xilinx documentation about their PCIe EP and I have a quesstion: I understand that the CPU, through the RC, controls the transfer (issuing a read or write command) but how...
  12. S

    Interconnection of multiple cores

    Hi, I have a design in which I use multiple cores for connecting to different interfaces: SPI, I2C, UART, etc. Each interface outputs the data to memory. I want to be able to both transmit data from the interface cores, read data from them and configure them (baud rate for example for UART)...
  13. S

    what does FPGA reset do? why reset?

    Ok, here's a very stupid question: Many of the IP Cores out there have a reset input signal. What's the purpose of this signal? Does it set the given core to it's initial state? Meaning all the registers go to their default values? Anything else besides that? How is the reset signal asserted...
  14. S

    FPGA SPI controller no microprocessor

    HI, I have a design in which I used the FPGA to access an outside the FPGA IC through SPI interface. On the FPGA I have a SPI master controller. The SPI controller has the SPI interface signals on one side (that accesses the IC's registers) and a address and data bus (sometimes Wishbone) on...

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