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  1. A

    [SOLVED] rising_edge() of switch....can we

    Provide some more details .. insufficient .. are you coding some logic to detect that?
  2. A

    4 bit full adder in verilog

    Always better to know some basics for the circuit. In case of a full adder we can implement it using two half adders and one OR gate. Verilog code and circuit details here Verilog rtl code for full-adder Full-adder circuit discussion.
  3. A

    FPGA related question.ALTERA kit is used

    Verilog rtl coding is not so difficult assuming you already have some coding background. Try this online tutorial. Good luck!
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    Parametrization in Verilog, sized and unsized vectors

    This is another way Refer example from this link for (i=0;i<64; i=i+1) memory_ram_q[i] <= 0; end
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    direct instantiation problem

    when synthesis works fine: I guess its still not reading the component from library. Instead its picking it from your component declaration. Are you sure the component resides within the library?
  6. A

    doubt regarding FPGA implementation

    May be this page can help you **broken link removed**
  7. A

    need verilog code for statemachine

    You can use case statements to generate packets in RTL Verilog or VHDL. You can find many examples over the internet. A sample is here Verilog Case statement to generate packets in a Testbench.
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    UART warning messages

    Is SRST asynchronous reset in your design? If so then false path all paths involving *srst. **broken link removed**
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    How to understand memory specification in Verilog?

    // Declare memory 64x8 bits = 512 bits or 64 bytes total reg [7:0] memory_ram_d [63:0]; reg [7:0] memory_ram_q [63:0]; Referred link Verilog memory code. Synchronous Random Access Memory (RAM). Testbench memory modeling.
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    Verilog synthesis problem "BLOCK RAM inferencing failed, output is not synchronous."

    Re: Verilog synthesis problem "BLOCK RAM inferencing failed, output is not synchronou I think what you are trying is to implement is a single port memory without proper control mechanism for reads. Synthesis tools fails, when they can't map the design to exiting library. Try adding rd control...
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    Any good resource - understanding pipeline

    There is not much to pipeline processing, quick reference Pipeline processing
  12. A

    VHDL code to a logic circuit

    You can still decrement on negative edge of clock or have a counter which is pure combinatorial .. We need to first know the entire code to know it in details. Its quite possible that the printed code is not correct.
  13. A

    VHDL code to a logic circuit

    Here is some explanation in blue, I have divided the code in three parts Part 1 ---- if (nReset = '0') then cnt <= (others => '0'); clk_en <= '1'; --'0'; ---------------------- At reset cnt = 0 and clk_en =1 is ---------------------- Part 2 ----- elsif (clk'event and clk = '1') then if (cnt =...
  14. A

    Any good resource - understanding pipeline

    There is a page on pipeline thats helps in general. Pipeline processing. In pipeline we basically divide the data processing into stages and push the inputs in a sequence through each stage.
  15. A

    Good Resource for FPGA example Code?

    Memories are usually good examples to synthesize. At end you can check the reports to see number of memory blocks your design used. A good link for **broken link removed**.
  16. A

    Good Resource for FPGA example Code?

    Are you looking for Verilog code examples that you can synthesize and layout on fpgas? Or you want to understand the fpga flow better?

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