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I just started studying PSL assertion for design verificaion. I am debugging a module which has programmable delay and it seems embeddeding PSL in VHDL code can be beneficial.
I want to describe a property of the data path of the module I am working on; I have two std_logic_vector...
As far as I know, they had to re-design the tool from the scratch because the existing tool could not handle very large 7 series FPGA effectively.
I've heard that it has plan-ahead like interface, but very different from ISE in many ways including the way to constraint a design...
I'm trying to infer dual port block memory on Virtex-2 part using ISE 10.1, but I got following error:
If I use ISE 13.4 and target other parts (I cannot target V2 on ISE13.4), I don't get the error.
Does anyone have experience with this error? How do we infer a dual port BRAM for V2 part...
Yes, what I know is based on synthesizing a circuit. Not just guessing. I was curious about exactly on this issue and tested it before. It was long time ago, though.
I thought you said that your answer still applies, didn't you?
Perhaps YOU should read what I wrote. I did not say that...
I've used Virtex-4 SX35 before. When I used 80%of LUT and 75% of register, it became unroute-able. I've used three BUFGs and a few BUFIOs.
In case of V4-Fx100, the maximum I could reach was less than those numbers, and I used more BUFGs.
I know it really depends on design, but I...
Altera provides a GPIO module which we can attach to Avalon bus. It comes with C functions we can use to write to and read from GPIO module. I mapped the pins of the GPIO I instantiated to the control lines I had...
I think you can get more information about it from help on the module.
Hm... Really? As far as I know, the implementation from case and if statements were different. I don't know how the synthesizer can create case statement from multiple if-elsif statement. I thought that was the reason designers prefer using case statement instead of if... is it not?
It will depend on many factors such as how much decoupling you have on the board, how many signals are switching at the same time, how fast they are switching, etc.
Simultaneous Switching Noise (SSN) can be analyzed in the tool FPGA vendors provide... once I had a problem with SSN on more than...
they implement different circuit.
If 'if' statement is used, it generates cascaded logic which checks for the 1st if statement condition, then next if statement condition, and so on.
If 'case' is used, all conditions in the statement have equal weight.
Oh, my bad. I thought the sum signal was not the part of the always statement.
Since both codes are synchronous and are only activated at the rising edge of clk signal, I would say they are identical.
Again, I am beginner in Verilog.... :razz:
When you open up the timing analyzer, you can run the analyzer by timing constraint. Also, you can set it up to display N worst timing paths.
Of course, the worst timing path is the bottle neck of the design.
A designer needs to specify false paths of the design. The tool does not know unless...
Yes, you can lock it in the ucf file. I don't know which device you are using, but there are number of accessible BUFGs from a pin. Why don't you select one which is not near your differential signal input?
As mentioned above, it is not straight-forward process. It does not convert any fancy Matlab function but some simple structure such as a state machine.
If you are not familiar with FPGAs or HDLs, it will be better to design using Simulink with FPGA vendor provided toolboxes such as DSP Builder...