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  1. N

    In cadence simulation how to introduce noise in current source?

    In cadence simulation i am trying to simulate a comparator. and i am using ideal current source (or measurement case off chip or external current). Now i want to simulate this comparator with current source having some noise so that i can verify the measurement case (external current source...
  2. N

    erroe while doing PEX using calibre in 65nm technology

    Re: error while doing PEX using calibre in 65nm technology Dear All i have design a transconductance amplifier. done with layout of it.. cleared DRC and LVS and PEX. in PEX i m getting some warning. i m not able to understand those warning i m attaching the file that shows warning
  3. N

    erroe while doing PEX using calibre in 65nm technology

    Dear All i have design a transconductance amplifier. done with layout of it.. cleared DRC and LVS and PEX. in PEX i m getting some warning. i m not able to understand those warning but because of these warning i m able to generate config view. i m attaching the error file
  4. N

    Cailbre PEX error with UMC65nm

    I am encountering the following error when I run extraction using Calibre v2011.4_14.13. Error while compiling rules file /Application/Cadence/CadencePDK/UMC65LLRF1P8M1T0F1U/RuleDecks/Calibre/G-DF-LOGIC/G-DF-LOGIC_MIXED_MODE65N-LL_LOW_K_CALIBRE-LVS-1.7-P1.txt: Error PEX5 on line 2302 of...
  5. N

    A fatal error in calibre PEX

    when i m running PEX using calibre i got fatal error. Rules file must contain a CAPACITANE ORDER statement. i m new in 65nm and i need to do layout of my circuit in 65nm. kindly help me.
  6. N

    [Moved]: LVS simulation in UMC 65nm technology using cadence

    hi i have simply design a inverter in 65nm and completed layout so that i can understand all layout process in 65nm. i have cleared DRC in LVS i have given the path of rules file. and for inputs i have given file path but i not able to give correct path for layout netlist so it is giving some...
  7. N

    IIP3 simulation of transconductance amplifier

    hi erikl thanks for sending me IIP3 simulation pdf. but pdf has mentioned how to simulate in agilent. but i m simulating in cadence. and i know the normal simulation of IIP3 by using PSS or QPSS. but i want to know the test bench of TCA IIP3 simulation, because in TCA input is voltage and output...
  8. N

    IIP3 simulation of transconductance amplifier

    hi all plz let me know the test bench for IIP3 simulation of TCA(transconductance amplifier)
  9. N

    tranconductance amplifier

    is design of CMFB for any amplifier by resistive divider, resistance value depends on frequency? how
  10. N

    tranconductance amplifier

    hi i have design a transconductor amplifier with CMFB. i have used 250K resistance for resistive divider from analog lib. now i want to replace it with UMC component. maximum resistance in UMC65nmlib is 124K so connected two resistance in series. but TCA performance degraded alot. m i doing...
  11. N

    trans impedance amplifer

    hi erikl i already posted schematic in above circuit now again i posting. plz let me know the problem
  12. N

    trans impedance amplifer

    hi everyone thanks for helping i have design TIA successfully. it is working fine 3dB BW is 15MHz. i have given isin at input. but if i m putting one more ac source voltage or current with frequency it is not working. and this ac source is not connected to TIA anywhere. why this problem is...
  13. N

    trans impedance amplifer

    diffrence parameter is frequency good plot is at 1.5MHz and bad plot at 2MHz
  14. N

    trans impedance amplifer

    i am attaching schematic and transient plot at 1.5M and 2M. now plz tell me what could be the problem
  15. N

    trans impedance amplifer

    hi i have designed a transimpedance amplifier having UGB 1GHZ and gain 60dB in AC analysis. but in transient analysis it is giving at output sin wave only upto 1.5MHz. after that frequency some sandom signal is coming why so?
  16. N

    mixer for front end receiver

    hi i have designed a passive mixer. for this individually i have tested TCA, TIA and switcing quard. all three are working fine individually. as i m trying to integrate its not working. so i reied one by one. now i got to know the problem. TIA is working upto only 2 MHZ. as i m putting any...
  17. N

    output voltage swing of two stage fully differential OPAMP

    hi everyone thanks for helping. now i want to ask question, it may be easy but i got confused. for simulating transimpedande amplifier in close loop i m using differential Isin. so resistance should be in series or parallel with Isin? i need to connect some input resistance because previous...
  18. N

    output voltage swing of two stage fully differential OPAMP

    Hi I couldn't understand how it is positive feedback . I have connected in- to out+. Plz explain me.
  19. N

    output voltage swing of two stage fully differential OPAMP

    when i m sweeping the input OPAMP is connected as a buffer so vin- is connected to vout+ for checking the output swing. ya this is also kind of transient if i m giving differential sin at input then transient is perfect.

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