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  1. C

    question about access time of sram

    I want to figure out how the port number of an sram give influence to the access time.for the following three kings of sram in asic 1)single port, write and read at different time 2)dual port, just two ports which each is like 1) 3)dual port, one for write and one for read using the same...
  2. C

    about cellbased digital backend

    After synthesising an rtl verilog to gate level, I use Astro to generate a layout gds file. The gds file passes the DRC checking, but I cannot get a circuit level netlist or schematic to run LVS/LPE checking. Questions are: 1.Is there needs to run LVS/LPE checking for cellbased design? 2.If...
  3. C

    what's the difference between VCS and VCSi ?

    vcs vcsi thanks and a similiar question about differnece between VCS-MX and VCS-MXi
  4. C

    synthesis with limited set of DC's .db lib

    I wan't to avoid using some cells in a .db lib is it possible? or how to create a customed .db lib ? thanks
  5. C

    peripheral registers in hdl, wonder a good style

    I'm designing a serial port controllor, so I'll maintain some peripheral registers. I wonder how to express peripheral registers in hdl. Mainly the controllor is divided into three module: cpu interface, the receiver and the transmitter registers can be sorted into three types by how they are...

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