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Please study on background methodology of DRC, LVS etc. Something like, how to you create a layout netlist for LVS, how the tool compares, how do you implement DRC rules etc.
Get a basic understanding of different rulefiles/runsets and be good at coding. Coding helps you to implement...
Filler cells are used for well continuity.
Imagine there are two standard cells with some space left in between them. so there is a discontinuity in the NWELL (for a NWELL bulk process) in this empty space, which affects your lithography step. In order avoid this, designer should make sure that...
In order to perform an ASIC physical design you need both Physical libs and logical libs of the standard cells and macros.
From your question, LEF constitutes physical part and .lib constitute logical part.
1. LEF : Library Exchange Format
CELL LEF : contains the physical description...
Wire is the physical part of your net. when your net is routed it will consists of different wires on different layers.
So wire capacitance is the capacitance calculated wrt ground (called ground capacitance) and the wrt other wires passing in parallel ( coupling capacitance)
DFT & DTFT are the nothing but how you express an irregular waveform in sine and cosine terms.
If you decompose your continuous periodic signal into sum of sine it is called "fourier series"
continuous non periodic : fourier transformation
Discrete periodic : Discrete fourier...
HFN happens during placement i.e. Pre-CTS.
So, area increase would be mainly due to clock tree balancing (inserting buffers in clock tree and inserting clock gating cells) and hold time optimization .
you need to netlist the properties during the extraction.
I am not sure about CALIBRE, but in hecules and ICV we use the properties option in the device extraction commands
You are correct. we use the worst case libs (max delay) for setup checksn and best case libs (min delay) for hold checks, because setup violations are caused due to slow data paths or fast clock paths and hold are caused due to fast data and slow clock paths.
If you set your operating...
"place_opt" command places the stdcells present in the netlist and adds extra buffers, inverters for the optimization.
it even performs high fan out synthesis for all high fan out nets, excluding clock nets.
Clock nets are treated as ideal nets.