# Search results

1. ### Physical verification- DRC, LVS

Hi, Please study on background methodology of DRC, LVS etc. Something like, how to you create a layout netlist for LVS, how the tool compares, how do you implement DRC rules etc. Get a basic understanding of different rulefiles/runsets and be good at coding. Coding helps you to implement...
2. ### what will happen if we dont use filler cells?

Filler cells are used for well continuity. Imagine there are two standard cells with some space left in between them. so there is a discontinuity in the NWELL (for a NWELL bulk process) in this empty space, which affects your lithography step. In order avoid this, designer should make sure that...
3. ### Need help regarding LEF and LIB files

Hi, In order to perform an ASIC physical design you need both Physical libs and logical libs of the standard cells and macros. From your question, LEF constitutes physical part and .lib constitute logical part. 1. LEF : Library Exchange Format CELL LEF : contains the physical description...
4. ### Wire Capacitance calculations formula

Wire is the physical part of your net. when your net is routed it will consists of different wires on different layers. So wire capacitance is the capacitance calculated wrt ground (called ground capacitance) and the wrt other wires passing in parallel ( coupling capacitance) so, wire...
5. ### What's main difference these two DFT and DTFT ?

DFT & DTFT are the nothing but how you express an irregular waveform in sine and cosine terms. If you decompose your continuous periodic signal into sum of sine it is called "fourier series" Similarly continuous non periodic : fourier transformation Discrete periodic : Discrete fourier...
6. ### export placement information- global routing

writing out DEF should work. Write out DEF, read it into another tool, complete your global routing, write DEF again and use it in your encounter.
7. ### Increase in Area during CTS

HFN happens during placement i.e. Pre-CTS. So, area increase would be mainly due to clock tree balancing (inserting buffers in clock tree and inserting clock gating cells) and hold time optimization . Thanks, Charan
8. ### Checking the capacitor width and length only using Calibre LVS

you need to netlist the properties during the extraction. I am not sure about CALIBRE, but in hecules and ICV we use the properties option in the device extraction commands eg : nmos ( properties {"length" double} {"width" double} ); Thanks.
9. ### Which std. lib we use for synthesis: worst, typ or best?

Hi, You are correct. we use the worst case libs (max delay) for setup checksn and best case libs (min delay) for hold checks, because setup violations are caused due to slow data paths or fast clock paths and hold are caused due to fast data and slow clock paths. If you set your operating...
10. ### cap/trans violations and DRC violations (using synopsys - IC Compiler)

Hi, use focal_opt with drc_pins and drc_nets switches to fix your maxcap and max trans violations. use can specify the violation as a file or as "all". thanks.
11. ### place_opt command - IC compiler (synopsys)

Hi, "place_opt" command places the stdcells present in the netlist and adds extra buffers, inverters for the optimization. it even performs high fan out synthesis for all high fan out nets, excluding clock nets. Clock nets are treated as ideal nets.
12. ### What are metal and via blockage layers

will route guides be checked for DRC violations?
13. ### What are metal and via blockage layers

hi, can u give me the difference between route guides and routing blockage w.r.t how they fix DRC violations? Thank you.
14. ### What are metal and via blockage layers

Hi, What are metal and via blockage layers and how are they different from normal metal layers? what are system metal blockages?
15. ### what are Tap cells and why they are used

thanks shivaram. i found it to be very helpful.
16. ### what are Tap cells and why they are used

Hello, can any one explain me clearly what are tap cells and how do they prevent latching? where they are inserted?