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    safe state machine problem

    others clause is not synthesized Hi all guys: I want ro generate a safe state machine, When the machine enter an unexpected state or an unreachable state, it can recove from these error state and run continuely. I have created a finite state machine by VHDL, synthesized by...
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    Problems about Altera LPM DCFIFO post simulation

    dcfifo problem first datas Hi, all guys Using the development tool provided by Altera, I generated a LPM DCFIFO as VHDL,whose depth is 128 and whose width is 16bits. Then I instantiated this DCFIFO in a top-level VHDL file, and there is only this one DCFIFO component in this top-level VHDL...
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    the way to generate register

    hi,all guys. Is there any way to generate regisers in CPLD or FPGA except using "signal" and "DFF" instantiation? Any help would be appreciated!
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    XST clock warnings in VHDL code

    Hi.everyone I have discribed a VHDL module. But when syhthesizing it by XST, there is a clock warning as follows: Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load |...
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    how to implement a frequence multiplier?

    hi all: An freqence signal want to be multiplied by FPGA. The input signal is(141K,817K), and the output frequence should be 32 * (141,817) or 128 *(141,817). Besides, DLL in virtex4 are required not to be used. Dose someone has good ideas? Any help would be appreciate! skycanny
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    how to make ISE and Modelsim work together?

    ise generate simprim I install ise6.2 and modelsim SE 6.0 and verify that they are able to work respectively as well as work well together when behavioral function simulating. However, there is a problem when ise and modelsim work together to make post simulation. Modelsim gives a hint as "#...
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    How to implement an absolute value in VHDL

    vhdl absolute value hi, all guys: In my project, I have to implement an absolute value. I use "abs" of VHDL in my project as "a <= abs(b);",where a and b have the same type, but it dose not work and the following is the error hint: abs can not have such operands in this context...
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    How to save Modelsim simulation graphics as a text file

    Hi, all guys: I use Modelsim to simulate my project. There are many data in the simlation graphics and I wanna save these many data as text mode such as *.txt file. Cloud this be implemented? Any help would be appreciate!
  9. S

    Modelsim error: Failed to access library 'simprim' at "simprim"

    Hi, all guys: I use ISE and Modelsim to develop FPGA. I have described a VHDL module and maded pre-simulation(behavioral simulation) by calling Modelsim in ISE , the pre-simulation result is corrsponding to my expectation. However when I call Modelsim to do post-place and route simulation...
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    How can I describe a ROM in VHDL?

    hi : all guys. I wanna discribe a ROM in VHDL , but VHDL is very new to me. And my this ROM is designed to store sine wave table. Can someone help me? Any help would be appreciate!
  11. S

    How to compute a sine wave in range of 0.005hz to 5 kHz in DDS?

    I am required to implement a sine wave generator and frequence range is 0.005hz to 5000hz. Given the clock is 100mhz, the problem is whether DDS can generator this frequence range sine wave. If it can, how many bits have the phase acc as well as how long sine table(a whole period) Is there...
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    XST synthesis problem

    I have instantiated 2 gf_mult(just a kind of multiplier)in a vhdl programme,but when synthesizing it, a warning occured: WARNING:Xst:1989 - Unit <rs_encoding>: instances <mult1>, <mult2> of unit <gf_mult> are equivalent, second instance is removed could anyone tell me how to solve this problem...
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    anyone can give me some helps?

    At present , I want to implement error corrcet coding by FPGA. I have learned vrilog HDL for several days and can use it to describe common digital circuits. Meanwhile,I am reqiued to use Xilinx device. I am able to design simple digital circuits by verilog and using ISE and download it to the...
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    Modelsim gives an unexpected simulating result,why?

    Verilog HDl and modelsim have been exposed to me for only one week. Today , I describe a Counter with 4 width using verilog HDL and simulate it by modelsim. However ,an unexpected simulating result occers.The following is my source verilog HDL counter: module counter(clk,clr,dir,ce,data_out)...
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    Problem with creating the test bench in ISE

    How can i go on? I have learned ISE of Xilinx for two days,and i do the job as the ISE Quick Start Tutorials. But I failed to continue when creating the test bench,and the hint is "No port signals detected". Where might be wrong? Could you tell me how to continue my work? Thanks

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