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    a problem about using verilog-a in HSIM simulation

    when i use laplace_nd function of verilog-a in hsim simulation, it cannt work,but using spectre simulation works well, what's the problem? i mean that when using hsim,the result assigned with laplace_nd will not change,it hold a constant my hsim is version 5.0 in linux.any one else met the...
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    questions about test of PLL and VCO

    1.about I/O circuit,How to choose the PAD for test?Beacause of the high speed output,do I have to choose LVDS PAD? and is the speed of the I/O important?If i decide to design PAD myself,what should I pay special attention for? 2.about package,because of the high speed output,do I have to use...
  3. Y

    questions about test of PLL and VCO

    1.about I/O circuit,How to choose the PAD for test?Beacause of the high speed output,do I have to choose LVDS PAD? and is the speed of the I/O important?If i decide to design PAD myself,what should I pay special attention for? 2.about package,because of the high speed output,do I have to use...
  4. Y

    How to speed-up the simulation of PLL

    It's lock time is about 100us I use nanosim to simulate it,and i set up properly for the trade-pff between accuracy and speed - i think so:) but the simulation is too slow,as pre-layout simulation,it takes 4 days to finish the simulation about 100us Can someone guys share some experiences about...
  5. Y

    how can use hspice in cadence ic50?

    i set the hspice in the ic50_install_dir correctly and can create the hspice netlist rightly,but can not simulate the circuit use hspice in ic50--install under redhat8. thank u:)

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