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    Start/Stop Counter Using Finite State Machine (Verilog)

    Hi, I'm trying to design a counter using finite state machine, with a start and a stop input. as output, I need the count value for calculating the time between start and stop signals. I calculated my max. count value as 90000, 17 bits (90 ms, with 1 MHz clock frequency). By the way I'm not...
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    [SOLVED] About DE0-Nano Board Configuration Device

    Hi, I have a DE0-Nano Board and when i turned its power off after programming then turned on again, it always loaded its default program. The user manual says that even the power is turned off, the information is retained in the configuration device (Spansion EPCS64). So, everytime i turned its...
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    [SOLVED] SPI slave module question

    Hi, i'm working for a SPI slave module on fpga with verilog. I have not used SPI before, so i don't know it well. I just read and looked some examples about it. http://www.fpga4fun.com/SPI2.html -> on this website it's very simple i think. but there are some points i couldn't understand. in...
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    [SOLVED] Rising Edge Detector Synchronization Problem

    hello, i designed an edge detector in verilog. it's RTL seems correct, but in simulation the output pulse is delayed. The examples on the internet, the pulse starts exactly with the rising edge of the clock signal. i used no delay in simulation. capture from the simulation and the code module...
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    [SOLVED] Verilog clock divider 50 MHz to 1 MHz

    hi, i'm new to the forum and FPGA. i'm designing a simple clock divider from 50 MHz as parameterized for a small part of a project. my code is successfully compiled but when i try to simulate it with quartus timing analyzer, the output clock is all X. i suppose there's something wrong with the...

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