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    How convert Oasis/calibre (.oas) to spef for timing analysis using cadence platform?

    I have extracted the def file of my processor in innovus/encounter/EDI and ported it to calibrewb in order to remove some dummy lines. Since calibre cannot generate def output, I saved the final design in oasis (.oas) format. Now I would like to import the oasis into cadence platform in order to...
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    Extracting area-delay pareto curve using Design compiler

    Hi, I need to extract area-delay pareto curve of one verilog netlist using design compiler. To achieve this I sweep the delay constraint using the following command: create_clock -name clk -period "sweeping_value" [get_ports xe_clk] and perform compile using: compile -ungroup_all...
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    Enumarating false paths using primetime based on -justify command

    Hi, I am trying to enumerate all false paths of the circuit using PrimeTime. I tried -true -false and -justify switches but it seems that these options have been made obsolete since the 2011.12 release of PrimeTime and are no longer supported. I am wondering whats the new commands? Thanks
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    find the name of all the primary inputs of a netlist in Modelsim using tcl

    Hi, I have a gate-level verilog netlist. In modelsim, I need to write a simple tcl code to find the name of all the primary inputs of the netlist. Then,on top of this list, I wanna randomly generate a logic value and assign it to each primary input that are obtained in the previous step. I am...
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    How to ungroup a design while preserving the full path name of intances (dc_sehll)?

    How to ungroup a design while preserving the full path of instances (dc_sehll)? Dear all, I am looking for a way to ungroup my design during synthesis flow while keep the full path of the intances. For example assume that I have: module sparc(); div div0 ( ) endmodule now when I use...
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    SDF error (encounter to primetime)

    Hi, I extracted a sdf file from encounter (after place&route step). However, when I wanna feed it into the primetime (using this command: read_sdf circuit.sdf) to extract the delay it gives some errors/warning such as: Information: Merging of parallel arcs is disabled by read_sdf...
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    Place a cell in a specefic region (SOC encounter)

    Hi All, Is there any way to force a specific cell gate to be placed (not to be placed) in a user-given region of the layout (using SOC encounter?) thanks V.
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    In system memory editor of Altera for Xilinx

    Hi!, I have been working with Altera FPGAs for a long time and now I have to deal with Xilinx ones. Until now, with Quartus II I have been able to manage the content of different registers and memories with 'In system memory editor' and I would like to do the same with Xilinx. I cannot...
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    Timing-aware Place&Route using SoC encounter

    Place&Route using SoC encounter Hi all, 1) Could you please let me know how can I consider timing-related constraints on place and route. In DC when we are performing synthesis, we can put a kind of constraint on the maximum delay between inputs and ouputs (e.g. delay between in1 and out1...
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    [SOLVED] How to convert verilog coding into hspice coding

    Hello, You shuold use a back-end software for converting it to hspice netlist. but if you dont have access to back-end tool you could synthesis it to a gate-level netlist by a front-end tool such as design compiler and then code a simple perl...... to convert the gate level netlist to hspice...
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    Timing report and finding ciritcal path in DC

    Hello, I need to extract X% most critical paths of a circuit using DC. I appreciate any suggestions/approach. thanks in advance.
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    synthesis just using nand or nor gates!

    Hello, Actually all the cells in the library have the dont-use propert except NAND2X0. because I just wanted to map the circuits to just nand gates. thanks ---------- Post added at 14:29 ---------- Previous post was at 14:19 ---------- Hello, I need to do some BILP (binary integer linear...
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    synthesis just using nand or nor gates!

    Hi, according to suggestions, I have used : set_dont_use {"saed90nm_max_nth_lvt/AND2X1_LVT"} set_dont_use {"saed90nm_max_nth_lvt/AND2X2_LVT"} set_dont_use {"saed90nm_max_nth_lvt/AND2X4_LVT"} set_dont_use {"saed90nm_max_nth_lvt/AND3X1_LVT"} set_dont_use {"saed90nm_max_nth_lvt/AND3X2_LVT"}...
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    synthesis just using nand or nor gates!

    Actually I have use this command. and Also I have wirte my own librar too: library(nand) { cell(NN2) { area : 2; pin(A) { direction : input; capacitance : 1; } pin(B) { direction : input; capacitance : 1; } pin(Z) { direction : output; function : "A*B"...
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    synthesis just using nand or nor gates!

    Hello I appreciate any help regarding synthesising a combinationals to only nand or nor gates using design compiler. regards, Farshad F

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