Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. A

    What and why is clock synthesis important?

    what is clock synthesis and why is it necessary?
  2. A

    Doubts about junction capacitance values in Tanner l-edit

    Doubts with using Tanner hi, i've been using tanner l-edit for a while now. in the setup of the layers, the ndiff and pdiff extraction layers are filled with the junction capacitance values. When a circuit is extracted, does the parasitic capacitance of a node, say output, contain the junction...
  3. A

    How to calculate node cap in HSPICE?

    When a netlist is extracted for a layout, what does the parasitic capacitances represent? Please check me on this: - for input caps, it doesn't contain gate cap. but contains all routing caps for that input. When simulated in HSPICE, the gate cap is calculated by the tool and added to the...

Part and Inventory Search