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Re: Performing read operation from a chip
Thanks sharath666 for the very quick response. I will do it this way. Is there any other way?
(i was imagining some vague and complex stuff like pushing the address into a queue and pop it one by one and driving on the third party chip interface)
I am writing RTL for a module, which interfaces with a different chip on the platform.
As part of the flow, this hardware module needs to do 10 register reads from the third party chip.
Read flow is =>
Module writes address, valid and rw signals on the first cycle and the...
I am going little slow :(.
1. Using 100M and 90deg phase shifted 100M clock, alternate nibbles has been sampled
2. using 180 deg phase shifted 100M clock I am able to sample the 8bit data.
Does that makes sense?
4 bit wide data bus needs to be transferred into slow clock domain. Sending clock is 100Mhz and receiving clock is 50MHz. The two clocks are synchronous clocks (clocks are derieved from the the same PLL). The 4 bit data changes every write clock cycle.
How to do a CDC without using FIFO?
Recently I had this question in an interview.
Request is 1 bit input to the DUT and grant is 1 bit output from the DUT. Design is when request goes high, ack has to follow request and should go high within 64 cycles. Similarly when request goes low, ack should go low within...
How should I understand input and output impedance in general? For example, the input impedance of an amplifier is this much and output impedance is this much. And what does that imply?
Say, input impedance of hte amp is very low/very high. And how does that matter when I design my...
linear amplifier design
when we say an amplifier is linear? Is it linear when gain is independent of the input voltage level?
Do we have any other metrics to qualify an amplifier as a linear one?
Highly appreciate your inputs.
"Clipping occurred on the 2nd input signal with lower common mode. This is because the common-source amplifier is an inverting structure. Lower input common mode voltage will produce a higher output common mode voltage as shown in the diagram."
Hi EECS4ever thanks for that note!! :)