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    Performing read operation from from a chop

    Re: Performing read operation from a chip Thanks sharath666 for the very quick response. I will do it this way. Is there any other way? (i was imagining some vague and complex stuff like pushing the address into a queue and pop it one by one and driving on the third party chip interface)
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    Performing read operation from from a chop

    Hello, I am writing RTL for a module, which interfaces with a different chip on the platform. As part of the flow, this hardware module needs to do 10 register reads from the third party chip. Read flow is => Module writes address, valid and rw signals on the first cycle and the...
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    input capacitane of a standard cell

    Hi, I have got a very basic question. What does input capacitance of a standard cell signify? What does it mean Thanks in advance. giri_lp
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    non-resettable flip-flop

    Hi, I have a generic question. Where do we use Non-resettable flip-flop in the design? What are the advantages of Non-resettable flip-flop -Giri
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    What is the most important SV and UVM?

    Start with System verilog and then go to methodology SV for verification by chris spear is a nice book.
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    [CDC] data transfer between synchronous clocks

    Hi ads-ee, I am going little slow :(. 1. Using 100M and 90deg phase shifted 100M clock, alternate nibbles has been sampled 2. using 180 deg phase shifted 100M clock I am able to sample the 8bit data. Does that makes sense?
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    [CDC] data transfer between synchronous clocks

    Thanks barry Thanks ads-ee, can you give a hint for the logic involved?
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    [CDC] data transfer between synchronous clocks

    4 bit wide data bus needs to be transferred into slow clock domain. Sending clock is 100Mhz and receiving clock is 50MHz. The two clocks are synchronous clocks (clocks are derieved from the the same PLL). The 4 bit data changes every write clock cycle. How to do a CDC without using FIFO?
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    asynchronous FIFO help

    Excellent analysis.. Thanks :0
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    Dynamic threads in system verilog

    Re: Dynamic threads in SystemVerilog Thank you. I will do some exercise staring at a piece of example and will get back if I have any questions
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    Dynamic threads in system verilog

    Hi All, I am learning SV and I am coming across the concept called dynamic threads. Can any one please explain me the concept of dynamic threads? -Giri
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    Plan for checker - Interview question

    Hi All, Recently I had this question in an interview. Request is 1 bit input to the DUT and grant is 1 bit output from the DUT. Design is when request goes high, ack has to follow request and should go high within 64 cycles. Similarly when request goes low, ack should go low within...
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    encyclopedia of electronic circuits

    Re: best book Try to google analog lectures from youtube and other sources. This may help a lot
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    Input and output impedance

    Hi, How should I understand input and output impedance in general? For example, the input impedance of an amplifier is this much and output impedance is this much. And what does that imply? Say, input impedance of hte amp is very low/very high. And how does that matter when I design my...
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    linear amplifier design. when we say an amplifier is linear?

    linear amplifier design when we say an amplifier is linear? Is it linear when gain is independent of the input voltage level? Do we have any other metrics to qualify an amplifier as a linear one? Highly appreciate your inputs. thanks
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    what is 3dB frequency

    what is 3db Hi, Can I apply this explanation here for amplifiers as well? Or is 3dB frequency diffarent for amplifiers? Help me here
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    Vin CM in differential amplifier

    "Clipping occurred on the 2nd input signal with lower common mode. This is because the common-source amplifier is an inverting structure. Lower input common mode voltage will produce a higher output common mode voltage as shown in the diagram." Hi EECS4ever thanks for that note!! :) Though I...
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    What's the advantage & disadvantage of using NMOS and PMOS cap in analog IC circuit?

    nmos in n well+capacitor What you mean by NMOS cap, PMOS cap? load capacitances are diffarent from parasitic caps. DO clarify here

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