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  1. Y

    Question about RC extraction

    you can just select the RCextrac in maxmum mode or minimun mode.
  2. Y

    Layout question about W/L of transistors

    Re: layout question this case is seldom appear in practice. what is your application?
  3. Y

    Designing a Current Steering DAC

    what frequency does the DAC work? and You can read some papers from Sansen's group. The key is the arrangement of the curren source array and the decoder arch. if it works at high frequency, the low power design of the decoder is not trivial.
  4. Y

    generation noise in cadence

    the first one is simple and flexible, i use it in my work. you explain it very clear, any problem then?
  5. Y

    How to simulate ring oscillator with 3 inverters?

    Re: Ring oscillator you can simulate the open loop ac gain of the delay cell chain, and find wether it is large enough for start-up. a simpler method is set the running step of tran small enough--less 1/10 period, and the noise of the numerical computation in simulator will make it oscillate...
  6. Y

    Openscshemes - Open-source schematic exchange

    it is really great!In the software and digital disign field,there are lots of sucessful samples--such as linux and opencores.org but there is some different for analog and RF,because it is too detial or somewhat else,so maybe we should try to think clearly that what kind of design is fit for...
  7. Y

    Symmetrical Load Ring Oscillator Design

    symmetric load high freq for this delay cell it's not diffcult to archieve the target,maybe you can add a voltage regulator for VCO to archieve high PSRR
  8. Y

    Anyone knows the .meas for measuring the PLL jitter

    trasient simulation itself don't include any noise source,so you cann't just use it to simulate jitter
  9. Y

    a problem about using verilog-a in HSIM simulation

    when i use laplace_nd function of verilog-a in hsim simulation, it cannt work,but using spectre simulation works well, what's the problem? i mean that when using hsim,the result assigned with laplace_nd will not change,it hold a constant my hsim is version 5.0 in linux.any one else met the...
  10. Y

    PLL without external loop filter

    i think that when you design your protype, you'd better use a filter with off-chip device--so that you can easily adjust your bandwidth when you debug your design. But when we do mass production,we would like to use on-chip filter for lower cost.
  11. Y

    How to put IO pads in a layout?

    Re: How to put IO pads Teddy: you said that just use last metal.do u mean that in the layout,do not full of the pad with each metal just as usually we do,in order to reduce the capacitive load? but i wonder that for the PAD the most of the load of it is the ESD circuit,so maybe i have to make...
  12. Y

    Help: how to print capacitance at a node in HSPICE?

    spice option captab as jinxingsun said,in .option line add this: "Captab",then in output .lis file ,hspice will list the cap of each node
  13. Y

    How to put IO pads in a layout?

    Re: How to put IO pads For high frenquency output,such as pll's output,can we use a PAD without the big capacitive load-ESD?How usually people design a PAD for RF purpose?:D
  14. Y

    How to put IO pads in a layout?

    Re: How to put IO pads In the prototype system design,can i just open a window for I/O connect and without ESD for output signal in order to output the signal at high frequency?
  15. Y

    Bond pad - passivation layer?

    you will have some PADS in the standard library,you can take it as reference...
  16. Y

    questions about test of PLL and VCO

    1.about I/O circuit,How to choose the PAD for test?Beacause of the high speed output,do I have to choose LVDS PAD? and is the speed of the I/O important?If i decide to design PAD myself,what should I pay special attention for? 2.about package,because of the high speed output,do I have to use...
  17. Y

    questions about test of PLL and VCO

    1.about I/O circuit,How to choose the PAD for test?Beacause of the high speed output,do I have to choose LVDS PAD? and is the speed of the I/O important?If i decide to design PAD myself,what should I pay special attention for? 2.about package,because of the high speed output,do I have to use...
  18. Y

    How to speed-up the simulation of PLL

    can some guys share me the info that: how long take you to simulate the PLL,including: 1.which kind of simulator do you use 2.what is type pll do you simulate 3.how do you set up the simulator thank u very much:D
  19. Y

    How to speed-up the simulation of PLL

    we now use nanosim,because we don't have the license for hsim. I have to do the post-layout sim,we are evaluating the jitter of this PLL in out application

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