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  1. S

    safe state machine problem

    others clause is not synthesized Hi all guys: I want ro generate a safe state machine, When the machine enter an unexpected state or an unreachable state, it can recove from these error state and run continuely. I have created a finite state machine by VHDL, synthesized by...
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    Problems about Altera LPM DCFIFO post simulation

    dcfifo problem first datas Hi, all guys Using the development tool provided by Altera, I generated a LPM DCFIFO as VHDL,whose depth is 128 and whose width is 16bits. Then I instantiated this DCFIFO in a top-level VHDL file, and there is only this one DCFIFO component in this top-level VHDL...
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    the way to generate register

    hi,all guys. Is there any way to generate regisers in CPLD or FPGA except using "signal" and "DFF" instantiation? Any help would be appreciated!
  4. S

    XST clock warnings in VHDL code

    Hi.everyone I have discribed a VHDL module. But when syhthesizing it by XST, there is a clock warning as follows: Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load |...
  5. S

    how to implement a frequence multiplier?

    hi all: An freqence signal want to be multiplied by FPGA. The input signal is(141K,817K), and the output frequence should be 32 * (141,817) or 128 *(141,817). Besides, DLL in virtex4 are required not to be used. Dose someone has good ideas? Any help would be appreciate! skycanny
  6. S

    how to make ISE and Modelsim work together?

    Thank for all your replies Late I found that I did not sepcify the correct path of Simulator when compling the libraries in ISE. Then I sepcified the proper path and repeated the process and this time it worked well. In the end. the libraries were compiled very well and ISE can work together...
  7. S

    how to make ISE and Modelsim work together?

    ise generate simprim I install ise6.2 and modelsim SE 6.0 and verify that they are able to work respectively as well as work well together when behavioral function simulating. However, there is a problem when ise and modelsim work together to make post simulation. Modelsim gives a hint as "#...
  8. S

    How to implement an absolute value in VHDL

    vhdl absolute value hi, all guys: In my project, I have to implement an absolute value. I use "abs" of VHDL in my project as "a <= abs(b);",where a and b have the same type, but it dose not work and the following is the error hint: abs can not have such operands in this context...
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    How to save Modelsim simulation graphics as a text file

    Hi, all guys: I use Modelsim to simulate my project. There are many data in the simlation graphics and I wanna save these many data as text mode such as *.txt file. Cloud this be implemented? Any help would be appreciate!
  10. S

    Modelsim error: Failed to access library 'simprim' at "simprim"

    Re: Modelsim problem Hi,kapil: I do not use any coregen module. And if so, behavioral simulation can not be done before compiling Xilinx Corelib. However,behavioral simulation have been done successfully. So, there must be other reasons. Could someone help me to solve this problem...
  11. S

    Modelsim error: Failed to access library 'simprim' at "simprim"

    Hi, all guys: I use ISE and Modelsim to develop FPGA. I have described a VHDL module and maded pre-simulation(behavioral simulation) by calling Modelsim in ISE , the pre-simulation result is corrsponding to my expectation. However when I call Modelsim to do post-place and route simulation...
  12. S

    How can I describe a ROM in VHDL?

    rom+vhdl Hi,jarodz: thank you I have done it by Matlab and added it to code
  13. S

    How can I describe a ROM in VHDL?

    vhdl code for rom thank all guys
  14. S

    How can I describe a ROM in VHDL?

    vhdl code rom hi,Renjith: You are right I am trying to implement a DDS and using Xilinx FPGA. However, I do not want to use CoreGen because the module CoreGen creates is hard to migrate to other target device. Could you help me? Any help would be appreciate!
  15. S

    How can I describe a ROM in VHDL?

    rom vhdl code thanks for replies The ROM I wanna describe is too large . Is there any method else? Any help would be appreciate!
  16. S

    How can I describe a ROM in VHDL?

    hi : all guys. I wanna discribe a ROM in VHDL , but VHDL is very new to me. And my this ROM is designed to store sine wave table. Can someone help me? Any help would be appreciate!
  17. S

    XST synthesis problem

    Thanks for replies If as you said, the sythesized resule is correspoding to my expectation?
  18. S

    How to compute a sine wave in range of 0.005hz to 5 kHz in DDS?

    Re: problem about DDS thanks for replies I have implemented it I divided the 100mhz clock to about 5mhz consequentialy the bits of phase accumulator droped. But the wave is not smooth observed through oscillograph because the LP has a higt stop frequence. The rom sine table is generated by...
  19. S

    How to compute a sine wave in range of 0.005hz to 5 kHz in DDS?

    problem about DDS Thanks for replies The critical problem is how many bits has the phase accmulator as well as how long table
  20. S

    How to compute a sine wave in range of 0.005hz to 5 kHz in DDS?

    I am required to implement a sine wave generator and frequence range is 0.005hz to 5000hz. Given the clock is 100mhz, the problem is whether DDS can generator this frequence range sine wave. If it can, how many bits have the phase acc as well as how long sine table(a whole period) Is there...

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