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  1. W

    Verification methodology of motion estimation in H.264/AVC

    Re: Verification methodology of motion estimation in H.264/A Thank you for your answer. I hope this way is good enough for verification, even it is quite difficult. Win2Y
  2. W

    Verification methodology of motion estimation in H.264/AVC

    Re: Verification methodology of motion estimation in H.264/A I used Verilog for RTL code. Motion estimation that I coded includes two parts: integer ME almost similar to JM reference software, and the other is fractional ME with new algorithm. However I want to make sure that RTL code with its...
  3. W

    Verification methodology of motion estimation in H.264/AVC

    Hi; I am currently doing Motion estimation (ME) in H.264/AVC. My question is about verification methodology of motion estimation in H.264/AVC. Who has some experiences in this please help me? Could anyone interested in discuss together? Any suggestion is welcome. Many thanks Win3Y
  4. W

    Making signal delay and hardwire cost issue? Thank you

    Something misunderstood here. I wanna output signal to be delayed by clock. But your way just takes input at posedge clk by some clockcycles, but does not delay it. Anyway, thank you for reply. W3Y
  5. W

    Making signal delay and hardwire cost issue? Thank you

    Hi everybody; I wanna make some control signals delayed 10 or more than 10 clock cycle. I just know the way like this: reg [Nbit - 1:0] control_1_delay,control_2_delay,control_3_delay...control_10_delay; always@(posedge CLK ore negedge nRESET) if (!nRESET) begin...
  6. W

    How to design a comparator N-bit with lowest cost?

    Thank you for your post. I also vote "helped" for you. This time I am doing something to reduce the hardware cost, not only these comparators. W3Y
  7. W

    How to design a comparator N-bit with lowest cost?

    Hi everybody; Is there any way to design a comparator N-bit with lowest cost? The comparator I made as following: input [N - 1:0] INP0, INP1; output [N - 1:0] MIN; assign MIN = (INP0 < INP1)? INP0:INP1; I wish to make another comparator that occupies smaller hardware cost. Thanks. W3Y.
  8. W

    Need a solution like multi-port SRAM, thank you!

    Hi everybody; I need the solution for this problem: Originally, I used 3 block RAMs (same content) with 3 separate Address reading signals. For saving reason, I just have only one block RAM, so what the solution for this problem in case budget cycle is limited (timing constrained). If it is...
  9. W

    Power Compiler- seperate license or is it in-built in ?

    Re: Power Compiler Just run "report_power" command, and the DC automatically invokes P/C if licensed.
  10. W

    Which one preferd if statement or assignment ?

    I mean that considering on BackEnd Engineering. If statement and assignment combinational logic, which one has more advantage. For example, comparing between them on the aspect of number of gate counts it may occupy and the delay it may have. Thank you W3Y
  11. W

    Is there any problem in a design with a lot of wires?

    Some given posts are really interesting. Thank you very much. To ljxp..: You are absolutely right ! I am that Back-End guy :D Is there anyone here who did successfully with [1023:0] bus wide ? W3Y
  12. W

    Is there any problem in a design with a lot of wires?

    Thank you for your suggestion. But I am still wondering whether my design has problem in such a big wire. Does It cause error? And even not working correctly? Win3Y
  13. W

    Is there any problem in a design with a lot of wires?

    Hi Everybody; I am going to fabricate my design using DC, Prime Time and Astro. But I am wondering there is any problem in the design with a lot of wires while implementing Back-End work? Is there anyone had experience with this? My design has 3 modules connected each other by some wires...
  14. W

    POWER consumption on BLOCK RAM?

    Sorry!!! It is my mistake when I estimate power without memory compiler. W3Y
  15. W

    Is data hazard in pipeline occurred or not in this case?

    Thank you very much for your idea. It is data hazard if reading from and writing data to the same register at the same time (same edge of clock), isn't it? One vote "helped" for you. W3Y
  16. W

    Is data hazard in pipeline occurred or not in this case?

    Hi Dears; Pipeline has 3 stage such as: Memory Read(MemR)(@slot0), ST1(@slot 1), Memory Write (MemW)(@slot2). At slot2: (MemW) Memory write back to register buffer A. But at the same time, at slot2: (MemR) memory read data from the same register buffer A. My doubt is that whether data hazard in...
  17. W

    POWER consumption on BLOCK RAM?

    I found the answer for it ^ ^. W3Y
  18. W

    how can I read saif file into modelsim

    Hi; Refer to this thread, it is really useful W3Y
  19. W

    How to minimise VCD file size for gate-level sim?

    Hi sjalloq; I think that dumpping vcd or saif by Nc verilog (Synopsys PLI) will take less time than your current way. Could you tell me the relation between the result of power estimated and amount of running time is? The result of power is increased directly proportional to amount of running...

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