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The way I did it currently is by looking for the DAC code that results a ToT that is the closest with the ToT at nominal simulation.
It catches 44 out of 50 samples, but I keep getting very high standard deviation even though I have already made my circuit larger.
How to simulate it correctly...
The example from here shows that how, by selecting the correct gm/Id or IC, we can minimize power consumption on common source amp (single MOSFET).
how can I do the same exploration, e.g., finding minimum power consumption, on a more complex circuit?
I have read Binkley's book. I...
In the system with negative feedback, what is described by G(s) actually? is it G(s)=A(s)/Y(s) ?
If I want to derive Y(s)/X(s), is it a correct way to derive G(s)=A(s)/Y(s) and then I can plug it in to the equation (8.2)?
With simple resistor as feedback, I usually derive the transfer function...
I have been looking for the paper you meant every now and then, but unfortunately I still cannot find it.
Could you give a more specific info about the paper?
here is the list of his publication.
I found this, but I am not sure this is what you were referring.
I run this command to get the CODE that I want:
xmin(abs(swapSweep(MC_DC_MISMATCH_UNTRIMMED "CODE")) 1 )
The result contain the mcparamset instead of only 9.
How can I get only the CODE, which 9 in this example?
What I did is simply clicking save script from GUI and running the script via CIW.
I use Assembler, Virtuoso 6.1.7 64b.
There this message in the main window when I run the script. This does not show up when I use the GUI.
I do not know whether it has something to do with the problem...
Thanks for the answer.
This was exactly what I did.
At the starting design point, the input differential pair dominates.
Then, I increased the size of input differential pair so it does not dominate mismatch.
This aligns with the discussion here.
Is this logic correct?
Apologize if this is kinda...
Thanks for the reply.
I am beginner here so I am still not sure what/how to decide. I understand your statement here, though.
Current-output DAC is used for trimming in my design, connected at the drain of the differential pair.
I use large diff-pair size so the input diff-pair does not...
I usually switch the view from Hierarchy Editor to do post-layout simulation.
Somehow ADE Asembler/Explorer stuck with the schematic view, it does not switch to the extraction view that I made.
If I chose ADE L in Hierarchy Editor, it works, i.e., I can see the netlist includes the parasitic...
Any tips to reduce the area of current-output current-steering DAC? or maybe better floorplan?
I feel that the current mirror arrays takes so much space but not sure how to make it better.
Here is my layout:
I followed your method and get some result.
I wonder why I need to choose, out of 32 offsets, the offset that is closest to the untrimmed mean instead of the one that is closest to zero.
The picture below shows 3 samples of MC result after post-processing. each line consists of 32...
I found the same author implemented comparators using the same process tech to detect the same polarity of signal but using different input devices.
From other publications, a good conclusion also cannot be made regarding the input device selection.
How should we choose the input device?
Hi, I wonder if you could explain a bit more in detail.
Sorry, I am really confuse with this setup.
What I do to get the offset is by sweeping the input voltage and then see at which value the output reaches 0.5VDD.
if I follow your plan, I would change the DAC settings in the Design Variables...
I need to simulate and show that the trimming circuit, i.e., 5bit current-output current-steering DAC, reduces the offset of a comparator.
But still confuse with the simulation setup.
I know how to simulate the input offset, but do not know how to simulate the comparator with the trimming...