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    What to do to become a good DSP engineer?

    Re: Hi.. everyone.. Hi Rajat, For becoming a good dsp engineer, you need to have all basics clear in your mind. All fundamentals to be clear. Maybe you can refer some books like Rabiner & Gold. Matlab is a tool. It is used for matrix operation initially.But now it has been used extensively to...
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    What are the methods for designing FIFO?

    Re: designing of FIFO Hi, The first thing you need to consider is the depth of the fifo.This is determined by the read and the write speed(Its the ratio). Since this is a synchronous fifo, so managing read and write pointers for accesing the fifo is not a tough job. Remember, write pointer...
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    What is the difference between verfication and testing?

    Re: q of verifiction? Hi, verification is done pre-silicon while testing is post-silicon. Verification is done in the pre-silicon stage to check the desired functionlity of the design. Testing is done in post-silicon stage to detect faults in manufecturing etc Regards, dak-ju
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    Register File declare/synthesis question

    Hi, DC will take care of it.So even if you declare 128 registers and use only 80, DC will optimize it. Regards, dak-ju
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    regarding internships

    Hi Anjali, I would like to know your interest like dsp in vlsi or purely analog Regards, Anup
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    Looking for documents about dual port FIFO

    Re: Dual port FIFO Hi Kumar_eee, I think any computer organization book will have fifo description.You can get idea about fifo from any standard computer organization book.However, for special type of fifo like asynchronous fifo, you can follow the Snug paper for the design of an asynchronous...
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    some command about DFT compiler

    Hi, Multiplexed flip-flop scan styles specifies that internal clocks driven by multiplexer (or multiple input gate) output pins are to be treated as separate clocks for the purpose of architecting scan chains. The -internal_clocks option is used by both command - set_scan_configuration and...
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    The green wire for color signal transmission in color TV

    Re: color TV Hi IanP, If you take a situation where R = 1, G = 0.1 & B = 1, then can we say that green signal is the biggest component of the whole equation? I think biggest component depends on the value for R, G & B. Best Regards, dak-ju
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    The green wire for color signal transmission in color TV

    Hi all, I have a querry on the color signal transmission in color TV. While transmission, the color difference signal is used using the red and the blue component.The green component is not used. My question is - why the green component is not used? Thanks and regards, dak-ju
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    information needed regarding regression testing

    Hi Srik, Regression is the process of running the entire test-base in batch mode. In a typical environment, you would run a regression after every significant change in the DUT model. Regards dak-ju
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    What does FDMA stand for?

    Re: fdma?? Hi , Actually I didn't mean freq. div. multiple access. what I know is - fdma is a type of dynamic memory access(dma). I want to know how is fdma different from dma. Regards dak-ju
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    what is hot-topic in digital design now?

    Hi, I think the hot topics in digital design are o. DSP based audio/video processing o. High Definition Television o. Low power mobile processors Regards dak-ju
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    Explain me concept of virtual clock in constraining design

    Re: virtual clock Hi, Defining virtual clock is simple. Do it as below : create_clock -name "clk_virtual" - period <value> -waveform {0 x} Best Regards, dak-ju
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    What does FDMA stand for?

    Hi, I want to know what is fdma? In what way Is it different from dma(dynamic mem. access)? Regards dak-ju
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    Explain me concept of virtual clock in constraining design

    virtual clock Hi can anyone explain me the concept of virtual clock in constraining a design? Regards dak-ju
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    false path in constraints

    Hi everyone, I want to know what are false path and why are they being set in constraining a design? Thanks in advance, dak-ju
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    Help needed--- Cmos physics and scaling effect

    You can refer to CMOS design by Kang & Lebelebici regards dak-ju
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    Problem with synthesis of VHDL code

    synthesis problem Pls have a look at the following code in vhdl if(clk'event and clk = 1) then x <= y; z <= x; end if; When I synthesize the code the rtl simulation shows z to be one clk cycle delayed version of y while in the netlist simulation it shows z to be two clk cycle...
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    plz provide inputs for coming interview

    Since you have been called for interview for frontend design, so the following area you should know properly a. IP(intellectual property basics) b. clear idea of setup and hold time c. little idea about synthesis d. design flow
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    What is the subthreshold region ?

    Re: cmos subthershold region subthreshold region is the region where a MOS is being operated below the threshold voltage.There are three operating region for MOS : subthreshold region, linear region and saturation region.You will find a detail description of the three region in the attached pdf...

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