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  1. javad

    Need info to design 1553 bus controller in VHDL

    Re: Arinc 1553 in VHDL 1553 Encoder/Decoder 1553 Encoder/Decoder
  2. javad

    FPGA + PC/104 Computer

    Hi all, I want to make an ISA interface between one Xilinx Virtex-II FPGA and a PC/104 single board computer. ISA bus is delivered through PC104 bus and is 5v, so I use level converters to mach FPGA 3.3v to this. The problem is when I place FPGA on ISA bus, the computer can not be started! (The...
  3. javad

    FPGA Development Board with 2 fast ethernet phys

    Hi all, Do you know a FPGA Development Board with 2 fast ethernet phys? Thanx.
  4. javad

    Spartan-3 I/O pins during configuration

    io pins of spartan3 Hi, How can I prevent FPGA I/O pins from going High(Active) during configuration process? Thanks.
  5. javad

    Virtex-II module error: The BSDL for device is out of date

    Re: ERROR with Configuration There are just two programmable devices on the board : FPGA and Programming Flash. I asked the vendor, but they didn't say any useful thing!
  6. javad

    lcd and keybord driven by fpga

    SEE "VGA/LCD Controller" project at opencores.org **broken link removed**
  7. javad

    Virtex-II module error: The BSDL for device is out of date

    ERROR with Configuration Hi All, I want to use a Virtex-II plug-in board module. The following error message occurs when I initialize the JTAG chain: "ERROR:IMPACT:477 - The BSDL for device 'unknown' is out of date. Please check your installation." After I select OK, It shows 9 "unknown"...
  8. javad


    xilinx xapp253 Did any one implement and use the 266 MBits/s DDR SDRAM Controller in xapp253?
  9. javad

    Need DDR SDRAM controller for Xilinx Virtex II or Spartan 3 FPGA

    Re: DDR SDRAM CONTROLLER OK! But It only supports Burst_Length = 2 and provides unidirectional DQS.
  10. javad

    Need DDR SDRAM controller for Xilinx Virtex II or Spartan 3 FPGA

    Hi all, I'm looking for a free good controller core for micron ddr sdram "mt46v16m16" to be implemented on xilinx virtex2 or spartan3 FPGA. I would be pleased if you help me to find that. If this core supports burst lenght = 8 and bidirectional DQS signal, it's much better for me. Thanks.
  11. javad

    Development Board with a lot of I/O

    Hi all, I'm looking for a development board for Xilinx Virtex family (V-II, V-II pro and specially V-4) with over 320 I/O connectors. I prefer the price less that $1000. Thanks. M. J.
  12. javad

    ATA Ultra DMA Controller on SPARTAN-3

    Hi All! I have designed an ATA UDMA controller on Xilinx Spartan-3 device. When I use 40-conductor cable, it works well (UDMA-2 is OK) but when I use 80-conductor cable, it does not work!(even UDMA-0) I think there is a problem with my IDE interface(physically). What do you think? Thanks all.
  13. javad

    Power supply for Xilinx Flash: XCF08PFS48C

    Hi all, What is the recommended power supply IC for this programming FLASH?
  14. javad

    What is the difference between ASIC flow and FPGA flow ?

    Re: ASIC & FPGA Read this article: **broken link removed** (specially see the figure 1)
  15. javad

    reading locked XC95144 - urgent help is needed!

    Are you sure? But I think this cpld is protected! I can't read with JTAG Port!
  16. javad

    reading locked XC95144 - urgent help is needed!

    Hi all! I have a board and a XILINX 95144 cpld is placed on it. I want to read back the content of this cpld. I think it is locked. Could you help me how to read this locked cpld? Thank you.
  17. javad

    Looking for free DES encryption ip to start practicing VHDL

    xapp270.zip SEE https://www.xilinx.com/bvdocs/appnotes/xapp270.pdf and xapp270.zip This is a "High-Speed DES and Triple DES Encryptor/Decryptor".
  18. javad

    Another way to configure Xilinx Spartan3 Starter Kit

    Hi all, I'm looking for another way except JTAG port to configure this kit. Can any one help me?
  19. javad


    Hi all, My Xilinx spartan3 starter kit doen't programmed via its JTAG3 cable. iMPACT says there are many unkown devices on jtag chain when I ask it to initialize JTAG chain. Chipscope fails on initializing too. I don't know where the problem is. How can I check that FPGA -itself- isn't damaged...
  20. javad

    Where to buy Altera and Xilinx FPGA chips in small amounts?

    Where to buy FPGA chips Go to avnet site at: www.em.avnet.com

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