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I wrote some RTL code, is there a quick way to tell me if there is any dead zone in the RTL w/o running any vector based Verilog simulation?
For example, if I accidentally tied clock input to a flop, I want to see some message like "The output of this flop will never toggle"
I try to sweep hold time (latency between data and clock edges for a flop) and measure the impact on clock -> output q delay
vclk clk 0 pwl (0ps 0v 20.0ns 0v '20.0ns+clk_slew' vdd_sup '30.0ns+clk_slew' vdd_sup '30.0ns+2*clk_slew' 0v '40.0ns+2*clk_slew' 0v '40.0ns+3*clk_slew' vdd_sup)
I am using Liberty Parser 2.5 from Synopsys to parse and process liberty files.
There is a Perl interface in the package so I use it to make my programming easy.
However, I found one issue in in this Perl interface: it's good to read .lib but when it comes to write out a modified liberty to a...
We tried nettran or icfb to convert a verilog gate-level netlist to spice transistor level netlist. However, we found these tools need the transistor information for standard cells to perform a complete translation. Otherwise, they simply do the syntax converting.
I just register a SolvNet account using my company's email and siteID.
It seems that there are many softwares downloadable and many documents/trainings too.
Anyone can tell me what's the proper (legal) way to take advantage of these resources?
Thanks a lot!
Someone on this forum said this can be done in Calibre but I don't have it.
I found that the parasitic R, Cs can be export in Astro, but not the design itself.
Maybe I missed something in Astro or I have to do it with some other tools?
Thanks for help!
I think the Vth should go down when scaling down to deeper sub-micron technology nodes for shorter channels and etc.
but Predictive Technology Model (PTM) assumes in the contrary direction
**broken link removed**
from 130nm to 22nm BSIM4 models, the vth0 parameter in model cards goes from...
In IEEE standard 1364, it says the following code
assign p = q;
q = 1;
#1 q = 0;
$display("At time: %t, the value is %f\n", $realtime, p);
could either display p as a "1" or "0". I can't understand why.
#1 q = 0...
I am using ncverilog (LDV4) to run a simulation with VPI functions (loadvpi option) but get the following errrors:
ncsim: relocation error: ./libvpi.so: undefined symbol: vpi_get_userdata
I checked vpi_get_userdata prototype in vpi_user.h:
XXTERN void *vpi_get_userdata...
I am using PLI1.0 for NCVerilog in a simple design but getting some errors.
Here is my PLI function in C:
double new_rise, new_fall;
gate = acc_handle_tfarg(1)...
I have a filter design in verilog and I want to compile it to Altera Stratix.
In Quartus II, I have an option that can balance mapping to Logic Elements or DSPs. If I choose LEs, no DSP will be used. All calculations are implmented in logics. If I choose DSP, most calculations will be mapped to...
I have a memory type signal:
wire signed [25:0] product[0:63];
when I try to add it to my waveform to see the value, some problem shows up:
whenever I add total node "product" or one element "product", the simulation always tells "can not find the node..."
Can anyone tell me how to add a...
I know it's pretty easy in other simulators like ncverilog, vcs. But Quartus simply ignores a lot of system tasks like "$fdisplay".
If I need to dump an output from simulation into a data file instead of show it in the waveform, what can I do?
Thanks a lot~