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    Verilog/VHDL editor in linux

    vim verilog +configuration I too found that xemacs with verilog_mode.el gives a colorful editing. You could possible customize the xemacs by using abbreviations. You can make your top level modules in 5 minutes otherwise could take days and prone to error.
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    What ASIC technology does Synopsis support?

    Re: About synopsis Synopsys has an array of tools. Useful for analog to digital and front end to back end design. However ther are very expensive and a small company generally will not be able to afford those expensive tools
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    Looking for a book about VHDL/Verilog ASIC design

    Re: Book Suggestion I found this book vey useful to learn verilog "Verilog HDL A guide to digital design and synthesis" by Samir Palnitkar
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    Which synthesis tool to use with a FPGA ?

    Use more flops and try to use pipeline concept. As these FPGA are generally very bad to do combinational logic.
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    Good combinational ATPG tools: Atalanta

    atalanta download atpg Iam unable to access this file...
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    Please introduce some good materials for Cadence back-end to

    Re: Please introduce some good materials for Cadence back-en As such I haven't come across any books which explicitly describe the cadence tools. One has to learn them through either Cadence training or peers. But looking at cadence docs could be a good start!!! Best of luck --phone
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    What's the best way to do Regression Testing?

    Use perl script for lot of options like running interactively, running regression/mini regression over a night and you could make the script to send an email to you after completing etc. Use c shell scripts for a just the job to get done ---Phone

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