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1. X and Z Propagation in Design

I think we are missing one more reason for the (X) propagation in designs, which is (SET-UP) and (HOLD) violation. I was reading an article which mentions cause of (X) propagation while doing (GLS - Gate Level Simulation) is timing violations. ---------- Post added at 14:27 ---------- Previous...
2. Digital Circuit For 3-Bit Verilog Counter

Hi All, What will be a digital circuit for a 3-Bit Verilog Counter. always @(posedge clk) begin if (reset == 1'b1) out <= 3'b000; else out <= out+1'b1; end
3. 4 - Bit Comparator using 2 - Bit Comparator

Hi All, How can we design 4 - Bit Comparator using 2 - Bit Comparator I will be thankful, If somebody can provide Digital Circuit Diagram
4. Asynchronous and Active Low Reset

Hi All, Can anybody tell Why RESET is Active Low and Asynchronous.

Hi All, Can any body help me in designing a 4-Bit Adder using 2-Bit Adder. Thanks
6. X and Z Propagation in Design

Suppose in waveform I am seeing X and Z propagating for a particular signal. What should be my approach towards debugging for the X and Z propagation. ---------- Post added at 17:13 ---------- Previous post was at 17:12 ---------- means X or Z propagation
7. X and Z Propagation in Design

Hi All, Can any body explain at What conditions X and Z propagates in design.
8. Interview Questions: 2 Always Block

What would be the value of B when A is 1 at (posedge of clk) always @ (posedge clk) b = a; always @ (posedge clk) b <= a;
9. How to add an element in the middle of Queue in System Verilog

Hi All, I have to add a element in the middle of queue How to add an element in the middle of Queue in System Verilog
10. Best Place For Monitors in System Verilog (Interface or Drivers)

Hi All, Can any body tell me Which is the best place to keep monitors in System Verilog Environment, Interfaces or Driver And Why ?
11. How to design 1 to 8 multiplier

Hi all, How to design 1 to 8 multiplier
12. $rise and$fell in assertions

Hi All, I have question. If there is a transition from z --> 1, 0 --> 1, x --> 1, z --> 0, 1 --> 0, x --> 0 What all the transitions will "$rise" and "$fell" will detect.
13. Limitation of ODD parity generator "circuit is attached

odd parity generator Hi All, This is ODD Parity Generator. Can any body tell me what's the limitation of this circuit. Regards
14. Circuit for Clock Divide by 5 and 50 % duty cycle

divide by 5 Hi, All can any body give me circuit.........for clock divide by 5 and 50% duty cycle. Regards
15. D-flip flop whose inverted output is connected to input

output no conected It will produce a clock half of the input clock. Edge will depend on the initial input you will give to the input "D", 0 or 1
16. Doc's needed for PLACE and ROUTE

Hi All, Can any body provide me some docs about Place and Route. I need them. Regards
17. T &gt;= Tcq + Tcomb + Tsetup - Tskew

effects of hold time violation Hi All, Can any body tell me 1) What causes HOLD VIOLATIONS in DESIGN. 2) How it effects DESIGN. 3) What changes need to be done to make DESIGN work.
18. Advantage of System C over System Verilog

Hi All, Can any body tell me What all the advantage is System C having over System Verilog. Regards
19. Problem with generating a 165 MHz in Time Scale

Hi All, I am having a problem which is I am having a CLOCK which has to Work on 165 MHz..... but Clock generator is generating a CLOCK of 164.8888 MHz due to which my FIFO are getting some time underflow or overflow depending on the data. Can any one tell me what's the solution to this...
20. Why use C++ in ASIC Verification

Hi All, Can any body tell me that What's the advantage or why we use C++ for ASIC Verification Regards