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I think we are missing one more reason for the (X) propagation in designs, which is (SET-UP) and (HOLD) violation. I was reading an article which mentions cause of (X) propagation while doing (GLS - Gate Level Simulation) is timing violations.
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Suppose in waveform I am seeing X and Z propagating for a particular signal.
What should be my approach towards debugging for the X and Z propagation.
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means X or Z propagation
I am having a problem which is
I am having a CLOCK which has to Work on 165 MHz.....
but Clock generator is generating a CLOCK of 164.8888 MHz due to which my FIFO are getting some time underflow or overflow depending on the data.
Can any one tell me what's the solution to this...