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thanks for valuable reply .
16 bit ddr3 working. so 0 to 15 data line will be there i cant able to route all in same layer .so shifted to next layer i know it will create some problem .my doubt is what kind of problem it will create or we can do route like that can you explain.
i have one reference board in that board they run over split plane ddr signal . i read some document same thing mentioned in that document should not route in above split plane.but i discuss with circuit designer low frequency we can run.can you some ref notes.
I am working on high speed board design .my doubt is avoid emi problem i provided full solid copper plane in external layer after completing routing.whether work out this method it will create any problem in design.
any alternate method.can you provide suggestion.
Thanks and regards...
Now i am working on DDR3 board its has 8 layer frequency range(1066 MHz). stripline used for signals routing. my doubt is one side full GND reference plane will be there and other side PWR split plane will be there. so signals crossing split plane any problem occur or it will work out.please...
pcb material selection
In high speed board design based on frequency and dielectric loss they are selecting pcb materials.
Any standard will be there in market like.
up to 6ghz use FR-4 material ,
above 6ghz use isola,
20ghz use rogger
please clear my question.
my doubt is what basis they selecting PCB material for pcb design.what parameter we should consider .little bit knowledge i have in this but not clear.
waiting valuable reply