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  1. V

    help! how to achieve KVMswitches in VHDL??

    PLEASE HELP !! THANK YOU VERY MUCH
  2. V

    Help!! In need of PS/2 VHDL source ! thanks!

    I am in need of source code of VHDL OF -- PS/2 and RS232 --Protocal!! if you have it ,or you know how to program it in vhdl , please help me!:| thank you very much!:D
  3. V

    how to use BUFGDLL of Xilinx FPGA? help!!!

    bufgdll how to use bufgdll of Spartan2 fpga ? my design includes a Top module which will call some small module and some other modules. when i use u1: bufgdll(clk_in,clk) ; there errors !!! how to use BUFGDLL ? thanks!
  4. V

    who may tell me what is the diffence between dsp and fpga ?

    that is what is the advantages of fpga and why I need fpga from XILINX OR ALTERA instead of DSP from TI ? thanks!!
  5. V

    Can not Download by Jtag!!!! IMPact hint that...

    " ERROR:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File. INFO:iMPACT:1578 - '1': Device IDCODE : 00000000000000000000000000000000 INFO:iMPACT:1579 - '1': Expected IDCODE: 000011000010100000010010011 " How to deal with this error...
  6. V

    Why iMPact detect a xcv100 while actually it is a xc2s100 ??

    HELP !!! why ? I know that spartan2 is made on the base of virtex, however In this condition , may xc2s100 work ? thanks!!!
  7. V

    who may kindly offer a VHDL source used for debouncing ?!

    Thanks a lot and a lot of thanks!! :)
  8. V

    May FIFO be read and writen simultaneously ?

    FIFO was made by BlockRAM out of Spartan2 (xilinx) , may this FIFO be read and be writen at the same time ? thanks.
  9. V

    Which USB chip is good for implementing connection to PC ?

    usb If you project use USB1.1 , then you may choose AN2131Q ;If you use USB2.0, then you may use CY7C68013 , both are easy to use and both form Cypress Co. Ltd. :)
  10. V

    Vhd & ImageProcess ?! help!!!

    :( :( May anybody help me with the urgent project----------- using vhdl to implement the "OTSU" image process , you may help me even you give me an idea or some resources in internet. :arrow: Thank you very very much.
  11. V

    May I design Video Acquisition System as following ?

    CCD Camera-->SAA7111A--> CPLD -->Cy7C68013 CCD Camera-->SAA7111A--> CPLD -->Cy7C68013 USB HUB-> PC CCD Camera-->SAA7111A--> CPLD -->Cy7C68013 CCD Camera-->SAA7111A-->...
  12. V

    Supply for FPGA(3.3V 2.5V)!?

    voltage regulator fpga May anybody offer some Schematics about Supply which offer 3.3V and 2.5V in FPGA System!? thanks. (Even you tell me the name of supply IC, you will help me a lot! :wink: )
  13. V

    Need resource/data abot Video Process using VHDL!?

    :( :( As a student form China, now I am working with some project about Video acquisition using SAA7111 , and I have to do some work about Video process using VHDL. I know that there must be lots of resource about thhis in WWW. However, I dont know where it is . So please help me...
  14. V

    [spartan2]How to deal with the VCCO ,Vref ?

    Need I connect each Vref? In what condition , may I use Vref pins as user IO? thanks!
  15. V

    [vhdl] how to implement PCI contrller ? where IP core??

    will you please how to make a PCI controller using VHDL ? MAY I get free open core ? thanks! :cry:
  16. V

    Where to find articles about VHDL and programs?

    Where to find VHDL ? www.xilinx.com is the very good resource of learning both vhdl and fpga and cpld @!!!!!! so great!!! enjoy it!
  17. V

    both rising_edge(clk) and faling_edge(clk) in one progrm,ok?

    rising_edge clk thank first. however, I heard that only coolrunner series have the ablity that may synthesis both rising_edge(clk) and falling_edge(clk), right? DO xilinx's FPGA have the same ablitiy ? thanks.
  18. V

    both rising_edge(clk) and faling_edge(clk) in one progrm,ok?

    rising_edge may I use rising_edge(clk) in process A, and at the same time using faling_edge(clk) in Process B??????? :cry: :cry: BOTH process A and process B in just one architecture! MAY I ? (spartan2 FPGA , in VHDL!) THANKS!
  19. V

    Timing Constraints, how to? thanks!

    what is the EXACT meaning of PERIOD ,FROM TO, OFFSET ? (using Xilinx SpartanII ). I know I should edit .UCF file , but how ?? :cry: I am a newbie , so thank you again for help me!!!
  20. V

    can I use LPM library in SPARTAN2 ? VHDL!!!??

    PLEASE hlep me!!! :cry:

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