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how to use bufgdll of Spartan2 fpga ?
my design includes a Top module which will call some small module and some other modules.
when i use
u1: bufgdll(clk_in,clk) ;
there errors !!!
how to use BUFGDLL ?
ERROR:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File.
INFO:iMPACT:1578 - '1': Device IDCODE :
INFO:iMPACT:1579 - '1': Expected IDCODE:
How to deal with this error...
May anybody help me with the urgent project-----------
using vhdl to implement the "OTSU" image process ,
you may help me even you give me an idea or some resources in internet.
Thank you very very much.
As a student form China, now I am working with some project about Video acquisition using SAA7111 , and I have to do some work about Video process using VHDL.
I know that there must be lots of resource about thhis in WWW.
However, I dont know where it is .
So please help me...
however, I heard that only coolrunner series have the ablity that may synthesis both rising_edge(clk) and falling_edge(clk), right?
DO xilinx's FPGA have the same ablitiy ?
may I use rising_edge(clk) in process A, and at the same time
using faling_edge(clk) in Process B??????? :cry: :cry:
BOTH process A and process B in just one architecture!
MAY I ?
(spartan2 FPGA , in VHDL!)