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    Question on Formal checking in Verification

    Hi all I am a graduate student specializing in VLSI design. I am trying to get acquainted with verification techniques and tools used in the industry. I am currently trying to understand the mathematical concepts of verification, like graphs, BDD, model checking, symbolic computation. But these...
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    Need good material on VLSI design Validation & Verificat

    Hi I am looking for some good course material on VLSI Design Validation and Verification.. Can you please help me in finding the same. Regards Sudarshan
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    Boundary scan IEEE 1149 for Memory test

    Hi all I am currently designing SRAM with BIST which will run March tests to test the SRAM. I came across the IEEE 1149 standard for testing but was not able to find good documentation for memory test using IEEE 1149 standard. Here r a few quick question. Can you please help me in clarifying...
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    Help required for Design for Testability

    Hi This is Sudarshan. I am a Graduate student and I will be doing a project on Design for testability using BIST. I have a few queries regarding the same and It will be really great if I can receive your help. Here are few of my queries: 1. I am completely new to Design for Testability. I...
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    Information required on Design for Testing

    Hi I am a Graduate student in VLSI design. I am looking for some good material and some suggestions on a project on Design for Testing. Can you please help me in finding the same.
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    combinatorial loop in VHDL code synthesis (Please Help)

    combinatorial loop Hi I am facing a warning which says "The following signals form a combinatorial loop". I am trying to build a combinational circuit (this is a part of a complete FSM ie a different process and will not have a clock interface). Here I am using a statement like ...
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    Query on VHDL 2-process modelling

    HI I am trying to write a 2-process model code for vhdl. i have defined a few signals to establish communication. Process 1 (Master) sets the signal which triggers the Process 2 (slave). Now I am trying to reset the same signal in the slave process, but this does not seem to be working. Can you...

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