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  1. S

    Queries : PFM mode Stability Analysis in DCDC converters.

    1. PFM mode loop is open loop or close loop? 2. Is it required to do Stability Analysis for PFM loop ? If No Why ?
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    What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifier

    What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifier Hi All, What will be the expression of Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifier. Here Gm is trans-conductance of the amplifier. If over all gain Av = (gm * Rs ) /(1+gm*Rs) &...
  3. S

    Analog parts in a CMOS Sensor..

    Hi All, I would like to know abot the all analog circuits parts present in a typical cmos sensor. Thanks
  4. S

    Topic for Analog circuit design paper.

    Hi All, I want to read and work on some analog design papers. I am just a beginner and reading razavi. Please suggess me some good topics of Analog circuit design. So that Thanks & Regards i can search in the proper direction. Sorabh
  5. S

    How to start learning ?

    Hi All, I am an analog layout designer (Beginner) and want to built my career in the field of Analog Design. It will be helpful if anyone tell me how to start and what should be the step-by-step procedure to make myself comfortable with the design issues. Thanks in Advance Sorabh
  6. S

    [SOLVED] Functions of skills. Script to show the timestamp and user

    Functions of skills. Hi, I want to make a skill script which shows the username and timestamp of last modified layout . Which functions i should use.
  7. S

    [SOLVED] What is the difference between contact and Via?

    contact & Via Hi, What is the difference between contact and Via. Can we place M1-poly, M2-M1, M3-M2 contacts one over each other so that they overlap in the layout?
  8. S

    [SOLVED] Common centroid cross-coupled differntial pair.

    Hi, I am just a beginner in layout field. I want to make layout of a differential pair by Common centroid cross-coupled approach. Each of the two transistors have 4 figures. which one of the following is best: ABAB BABA or ABBA BAAB or ABBA ABBA Thnx
  9. S

    [SOLVED] Skill language for making layouts.

    How to use skill or any other scripting language to make layout in cadence virtuso layout suit.
  10. S

    Dual-threshold Model files.

    Hello everyone, In case of Spice models, i want to know about dual threshold vtg logic...Means two threshold in single circuit.... Is it required separate special model files having dual threshold vtg or any other method is there ? In a paper the low Vth is 0.2v while high Vth is...
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    [SOLVED] Hspice netlist to Layout ...

    hspice netlist Hello everyone, I want to go from HSpice netlist to Layout and want to calculate area. Could anybody tell me please the exact flow (means procedure) & tools required in that flow. Thanks & Regards SKamthey
  12. S

    [SOLVED] errors while running Tmax during DRC

    drc rules tetramax Hi everyone, I am getting some errors while running Tmax during DRC: How to overcome these errors.. DRC> set drc /home/student1/sk4xilinx/proj4/proj4stil.spf run drc ------------------------------------------------------------------------------...
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    [SOLVED] TetraMax help.. How to get Verilog Model libraries

    tetramax verilog syntax Hi everyone, I need verilog model libraries for tetramax.. How can i get that.. Are they present in synopsys tool ..or i have to down load them.. Thanks & Regards SKamthey
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    [SOLVED] Mentor FastScan tool help..!

    mentor fastscan Hi everyone, I need help to run FASTSCAN tool of Mentor Graphic to generate Test pattern for a Combinational circuit. Could anybody help me please.. Thanks & Regards Skamthey
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    [SOLVED] Good Books for Verilog & VHDl ?

    quaturs software Hi, please suggess me some good books for verilog & VHDL. Thankis & Regards Skamthey
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    [SOLVED] Any Book to learnTetraMax..

    Hi everyone, I am looking for a book to learn TetraMax tool. if anybody knows please help me. Thanks & Regards skamthey
  17. S

    Hspice Model File Help...

    Hi Everyone, I want to use dual-threshold logic in my transistor level circuit using HSpice. My query is : Is there any seperate model files ( TSMC or UMC or anything else ) for Dual-Threshold logic purpose.
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    Tetramax GUI Help..variable "TMAX_RF" is undefined

    Tetramax Help.. Hi , As Tetramax GUI comes, it's not responding to any commands, even help topics too. It's showing text like: variable "TMAX_RF" is undefined. etc If possible please reply.
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    hspice help.DOMINO ckt in Hspiceusing TSMC 0.18 model

    hspice help. Hi everyone, I am just simulation an DOMINO ckt in Hspiceusing TSMC 0.18 model . In documents the W may vary from 1.5 to 8u, but as i m increasing w above 2.3 µ the tphl & tplh calculations failed, because the output in milivolts. But in case of a simple...
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    How to use Verilog UDP in other modules?

    Hi, I want to use an UDP say "primitive.v" in any other module. How can i do this. I just add that primitive.v file into existing module file, and make instantiation but it's not working.

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