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What will be the Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifier
What will be the expression of Gm, Rout & Av= Gm * Rout of a single-stage Common Drain amplifier.
Here Gm is trans-conductance of the amplifier.
If over all gain Av = (gm * Rs ) /(1+gm*Rs) &...
I want to read and work on some analog design papers. I am just a beginner and reading razavi. Please suggess me some good topics of Analog circuit design. So that
Thanks & Regards i can search in the proper direction.
I am an analog layout designer (Beginner) and want to built my career in the field of Analog Design.
It will be helpful if anyone tell me how to start and what should be the step-by-step procedure to make myself comfortable with the design issues.
Thanks in Advance
I am just a beginner in layout field.
I want to make layout of a differential pair by Common centroid cross-coupled approach.
Each of the two transistors have 4 figures.
which one of the following is best:
In case of Spice models, i want to know about dual threshold vtg logic...Means two threshold in single circuit.... Is it required separate special model files having dual threshold vtg or any other method is there ?
In a paper the low Vth is 0.2v while high Vth is...
I want to go from HSpice netlist to Layout and want to calculate area.
Could anybody tell me please the exact flow (means procedure) & tools required in that flow.
Thanks & Regards
drc rules tetramax
I am getting some errors while running Tmax during DRC:
How to overcome these errors..
DRC> set drc /home/student1/sk4xilinx/proj4/proj4stil.spf
I want to use dual-threshold logic in my transistor level circuit using HSpice.
My query is : Is there any seperate model files ( TSMC or UMC or anything else ) for Dual-Threshold logic purpose.
I am just simulation an DOMINO ckt in Hspiceusing TSMC 0.18 model .
In documents the W may vary from 1.5 to 8u, but as i m increasing w above 2.3 µ the tphl & tplh calculations failed, because the output in milivolts.
But in case of a simple...