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  1. M

    about how to access DDR SDRAM

    U r question is vague,can u explain in more detail Added after 1 minutes: U r question is vague can u put ur points in detail
  2. M

    Why can't we have intra assignment delay in Verilog code?

    why can't we have intra assignemt delay in continuous statement in the verilog code like assign x = #5 clk
  3. M

    what is the need of Data Mask in DDR SDRAM

    data mask pin Actually data mask is use for the data masking the data byte by using the byte enable .
  4. M

    What is the main use of PERL in VLSI?

    application of perl in vlsi PERL:practical enquiry and reporting language .Its a scripting language.IN verilog mainly in verifying instead of doing things manually scripting makes things easy Go to oubook.com abd u can find lot of books
  5. M

    how to go Binary addition in vhdl with vectors

    vhdl binary addition include the foolowing libraries arith and unsigned too then they will executed
  6. M

    Why the simulation time increases when we list all the events in the sensitivity list

    why the simulation time increases when we do list all the events in the sensitivity lists
  7. M

    Definition of setup and hold time

    Re: floating point multiply
  8. M

    Small depth Async FIFO

    U can have in xilinx material about asynchronus fifo
  9. M

    New to this Group....

    plz suggest me a good book for ASIC design..........

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