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    Problem in MMSIM 7.1 and ibm

    Hi everybody, I am doing some test design (an inverter) in order to get used to the IBM 90nm process cms9flp. I pass succesfully drc and lvs in assura and calibre and the assura qrc also ends succesfully. the problem arises when i run a DC simulation including the parasitics, using av_extracted...
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    Virtuoso hierarchical layout design

    Hi to all! I have the following problem. I made a layout component in Virtuoso that is simply a stack of metals with vias between them. When I use this component in my main layout design in order to connect two metals the connectivity checker shows that they are not connected. Is there...
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    question about transmission lines for a distributed VCO

    Hello everyone. I’m trying to design a cmos distributed differential VCO for a project, which means 2 parallel microstrip lines for the drain load and another 2 microstrip lines for the gate line. For the inverter i’m using the “delay variation by positive feedback” tuning technique, proposed...
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    LVS problem in nfets in ibm process

    Hello, I am designing a LNA circuit using IBM 0.5um sige5am process. I am in the LVS process. I face the following problem. In my design I use both nmos kai pmos transistors. The pmos (pfetx in the process) has four terminals both in design and the layout and passes the LVS check without...
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    LVS problem about multifingered mos

    Hello I am designing a circuit in IBM 0.5 sige5am technology and I have the following problems when conducting diva lvs check. The design has a single mosfet. When the number of fingers of the mos is 1 then the lvs check gives netlist match. However when increasing the number of fingers, for...
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    Strobed noise analysis: noise skip count & number of poi

    Strobed noise analysis Hi to all, I want to specify the edge-to-edge jitter of a frequency divider. I have read the paper of Ken Kundert "Predicting the Phase noise and jitter of PLL - based synthesizers" (can be found at www.designers-guide.org ) which suggests the use of pnoise analysis in...
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    Chipset or a set of modules? Which to use?

    Hi to all, I want to design a communication system in order to get some measurements. I can either buy the required chips and connect them on a pcb or buy the items as modules and connect them via coaxial cable. Which solution do you think is better and why? Thanks in advqnce for your help.
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    Phase Noise of A Closed Loop System (PLL)

    Hi to all, I would like to ask how to calculate the phase noise at the output of a closed loop system such as a PLL. I have seen the method described in https://www.designers-guide.org/ by Ken Kundert. He incorporates the jitter in the behavioural model of the subsystems of the PLL and...
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    How to insert analog blocks in Verilog-A in ADS?

    ads verilog Hi, I want to insert some analog blocks written in Verilog-a code in ADS2004A. I have done this in Cadence but in ADS there should be a different process. My question so, is how to insert the blocks. There is a folder named "veriloga" where the veriloga files are stored but then...
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    Phase noise in a PLL using @DS

    Hi to all, I have designed a ring oscillator in ADS and I simulate its phase noise using harmonic balance analysis. When I use the specific oscillator in a PLL, with a divider, phase detector and filter, I want to simulate the resulting phase noise in its output. However this is not possible in...
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    Looking for commercial product for 802.11

    Hi, I am looking for a commercial product that implements the 802.11 protocol. Moreover, I want it to have the possiblillity to overcome the existing MAC protocol and use another one, created by me. As I have searched to the net I haven't found such possibillity. If anynone knows such a product...
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    Help me with variable gain LNA modeling in ADS

    LNA modeling in ADS Hi to all, I want to simulate a commercial variable gain LNA in ADS. The specifications of the model are listed in the picture. For further information you can use the link: **broken link removed** How can I do this because in ADS there is no a single amplifier model that...
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    Port refinement, process abc3d error in HFSS 9.2

    abc3d problem in HFSS Hi to all, I am a newbie in HFSS 9.2. I have designed an inductor which is attached to this message and during the analysis I get the following message: "[error] Port refinement, process abc3d : There are no tetrahedral faces assigned to boundary "PerfE1". Since boundary...
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    Label short in Cadence Virtuoso

    Hi, I have designed a spiral inductor in Cadence Virtuoso and in the Schematics I designed the equivalent pi-circuit with lumped passive elements. I want to make LVS. The layout passes successfully the DRC check. However in after the LVS running I get the message that there is a short between...
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    CMOS LC Oscillator output buffer

    lc oscillator buffer Hello, I have designed a crosscoupled LC oscillator as shown in the following picture which operates at 1.8GHz, in 3V supply voltage and has a sinusoidal peak to peak voltage swing of 2V. My question concerns the output buffer that follows the oscillator core. What kind of...
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    Ads time domail reflectometry

    Hi everyone, I want to simulate transmission line discontinuities in ADS for a project using transission line reflectometry. How can I do that in ADS? Thanks a lot!

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