Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. G

    Cadence layout NMOS p substrate connection

    Iam drawing a layout in Cadence for a 2 input nand gate.In the Pull down network i used a p substrate for each of the NMOS. For the lower NMOS i connected the substrate to Ground.But, when i connect the substrate of the upper NMOS to the its source as in the schematic,i get the errors "p...
  2. G

    nested for loops running forever

    This is the part of my code for histogram segmentation. It has to read data from in[i][j] into a temporary variable n which is the intensity of that pixel.Then it has to increment the nth bit of the hist vector by 1 so that at the end the vector hist has the requires histogram values.But the...

Part and Inventory Search