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In many COMS circuits, the ESD protection circuits are offen constructed with large NMOS or PMOS. I want to know what is the relationship between the ESD robustness and the sizes of these MOS transistors. Is there any papers or documents about this question? Or any simulation method?
I have a partial directory of what used to be a part of cadence library
designed on an old version of cadence (probably in 1990). A lot of files are missing, cds.lib is also missing. The directories I have are named after the respective subcircuits they belong to. Each directory has subfolders...