Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi-Active Latch with Asyncnous Lo-Active Reset Digital Standard Cell Characterization
can we use transimission gate in a standard cell design ?
and what are the advantages on nand gate based logic ?
the above schematic represents Latch with Asyncnous Lo-Active Reset using transmission gate...
AS part of my project im charecterizing the standard cell iv mentioned to start with i need a schematic i have the schematic in transmision gates
suggest me or guid me regading this is the circuit correct ?
I read the UG ,thank for the information,i finally found the flow to follow on my project which is characterizing a standard cell "asynchronous latch"
1.schematic ----->tool CDesigner SE
2.layout ----->tool CDesigner LE
4.RC extraction Star RC...