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    SIMULATION MODEL for 32M Flash

    samsung nand flash model I think the contents of the NAND flash model is protected using Cadence's approach. And the modelsim could not read that in. You need to use Cadence's Verilog-XL or NC-Verilog to run the simulation.
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    Dump ".fsdb" in modelsim NT version?

    dump fsdb in modelsim If you don't need to use additional PLI, you are supposed to be able to use the included novas.dll to dump fsdb file. Look for the document in your installation.
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    How to deal with high-fanout nets using DC

    high-fanout net + synthesis Actually it will depend how many cells the reset signal is gonig to. If you want to let the synospys DC to add buffers for reset signal, use set_max_fanout 20 your_design, something like that. And use balance_buffer command to insert reset buffer after synthesis...
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    Already have FPGA compiler, why need Design Compiler (DC)?

    Design Compiler Can design compiler do FPGA synthesis? I mean if there are the library cells for those FPGA devices, could we use DC instead of FPGA compiler. I am more familar with traditional scripts than the graphics GUI.
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    Looking for FPGA tools that does DFT

    FPGA with DFT Sorry fo the confusion. What I want is Windows-based FPGA tools that can not only translate RTL to FPGA cells but also insert the scan-chain (or JTAG). We would like to verify that the JTAG (or the scan chain) is inserted correctly and the system can work with external...
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    Help me solve current leakage in a design

    Thanks for the suggestions Thanks you all for the suggestions.
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    Poll: ASIC design tools for Solaris

    Design database management How about design database management tool? Will RCS or VCS be just fine? Or is there any good one?
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    Looking for FPGA tools that does DFT

    FPGA tools that does DFT Is there any FPGA tools that can help me insert scan chain for DFT?
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    Help me solve current leakage in a design

    characterizing memory current leakage with hsim I have a design which I found uses excessive current while in suspend mode when clock is turned off. Is there any good tool that can help me catch the problem? RTL level or transistor level will be just fine. Of course I didn't want to run...
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    Dump ".fsdb" in modelsim NT version?

    creating fsdb files in modelsim You need to modify the modelsim.ini file to add a line like this: Veriuser = novas.dll Also you need to set LD_LIBRARY_PATH to point to the novas.dll file.

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